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SerDes鏈路協(xié)同仿真與無(wú)源鏈路優(yōu)化設(shè)計(jì)
電子技術(shù)應(yīng)用
杜審言,付雷雷
高澈科技(上海)有限公司
摘要: 隨著SerDes鏈路信號(hào)傳輸速率的提升,信道鏈路經(jīng)過(guò)芯片封裝和印刷電路板過(guò)孔、AC電容和連接器等,會(huì)導(dǎo)致信號(hào)完整性(Signal Integrity, SI)挑戰(zhàn)進(jìn)一步增大。提出基于SerDes 32 Gbps-NRZ信道傳輸系統(tǒng),優(yōu)化無(wú)源信道中的BGA過(guò)孔、AC耦合電容焊盤(pán)、FMC連接器(FPGA Mezzanine Card Connector)處Pin腳設(shè)計(jì),提升了通道阻抗的一致性,建立了更為準(zhǔn)確的無(wú)源鏈路通道模型,并結(jié)合芯片有源IBIS-AMI模型,對(duì)比分析優(yōu)化前后鏈路信道對(duì)眼圖的影響,保證了32 Gbps-NRZ高速信號(hào)的穩(wěn)定傳輸。
中圖分類(lèi)號(hào):TN919;TP336 文獻(xiàn)標(biāo)志碼:A DOI: 10.16157/j.issn.0258-7998.245386
中文引用格式: 杜審言,付雷雷. SerDes鏈路協(xié)同仿真與無(wú)源鏈路優(yōu)化設(shè)計(jì)[J]. 電子技術(shù)應(yīng)用,2025,51(1):25-28.
英文引用格式: Du Shenyan,F(xiàn)u Leilei. SerDes link co-simulation and passive link optimization design[J]. Application of Electronic Technique,2025,51(1):25-28.
SerDes link co-simulation and passive link optimization design
Du Shenyan,F(xiàn)u Leilei
Celestial Microsystems(Shanghai) Co., LTD.
Abstract: As the signal transmission rate of the SerDes link increases, the signal integrity (SI) challenge increases further as the channel link passes through PKG and PCB boards, through holes, AC capacitors and connectors. This paper provides a transmission system based on SerDes 32 Gbps-NRZ channel, optimizes the design of BGA holes in passive channels, AC coupling capacitor pad, and Pin pins of FMC connectors, improves the impedance consistency in channels, and establishes a more accurate passive link channel model, combined with the active IBIS-AMI model of the chip, the influence of the optimized channel on the eye image is compared and analyzed, which ensures the stable transmission of 32 Gbps-NRZ high-speed signal.
Key words : SerDes;passive link analysis;eye image simulation;IBIS-AMI model

引言

隨著電子芯片系統(tǒng)的小型化和高度集成化,PCB上傳輸信號(hào)速率的不斷增加,加上PCB板層數(shù)不斷增多,鏈路中不可避免地需要過(guò)孔換層,而長(zhǎng)距離跨板傳輸信號(hào)也需要使用連接器和AC耦合電容等器件。所以針對(duì)SerDes信號(hào)系統(tǒng)的信號(hào)完整性仿真設(shè)計(jì)分析變得更加重要,在信道鏈路中,過(guò)孔不能僅僅當(dāng)作金屬過(guò)孔,同時(shí)也要考慮過(guò)孔的焊盤(pán)、反焊盤(pán)以及殘樁等帶來(lái)的電容寄生效應(yīng)影響[1]。所以鏈路系統(tǒng)設(shè)計(jì),尤其是對(duì)高速SerDes進(jìn)行全鏈路設(shè)計(jì)時(shí),必須對(duì)其通信信道進(jìn)行信號(hào)完整性SI仿真分析。

本文基于3D電磁仿真軟件,結(jié)合芯片有源IBIS-AMI模型,對(duì)SerDes 32 Gbps-NRZ高速信號(hào)進(jìn)行信號(hào)完整性仿真分析。其中無(wú)源仿真優(yōu)化包括: 芯片側(cè)BGA過(guò)孔優(yōu)化,通道中AC耦合電容焊盤(pán)設(shè)計(jì)優(yōu)化、FMC連接器處Pin腳優(yōu)化、SMA接頭優(yōu)化,最終無(wú)源電磁仿真中的RLCG或S參數(shù)模型結(jié)合有源IBIS-AMI(Algorithmic Modeling Interface)模型進(jìn)行仿真,在信道RX接收端觀測(cè)分析眼圖質(zhì)量。


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http://ihrv.cn/resource/share/2000006277


作者信息:

杜審言,付雷雷

(高澈科技(上海)有限公司,上海 200120)


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