中圖分類(lèi)號(hào)：TN710 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234746
中文引用格式： 付然，孫晨陽(yáng)，劉芳，等. 基于JESD204B接口的波形產(chǎn)生FPGA設(shè)計(jì)[J]. 電子技術(shù)應(yīng)用，2024，50(7)：103-106.
英文引用格式： Fu Ran，Sun Chenyang，Liu Fang，et al. FPGA design for waveform generation based on JESD204B interface[J]. Application of Electronic Technique，2024，50(7)：103-106.

FPGA design for waveform generation based on JESD204B interface

Abstract： An FPGA design for waveform generation based on JESD204B interface is introduced. This design mainly consists of FPGA, DAC, DDR3 and network chips, and realizes the generation of intermediate frequency signals with dual channel frequency range of 2 GHz to 3.5 GHz. FPGA and DAC are linked through high-speed serial interface JESD204B, realizing waveform generation, digital up-conversion and analog conversion, network chips and DDR3 are used for transmitting and storing special waveforms. The article provides a detailed introduction to key technologies such as JESD204B interface clock synchronization design, DDS signal generator, digital waveform reception, storage, and transmission. Finally, the reliability of the FPGA design is verified by the intermediate frequency signal captured by the DAC output through a spectrum analyzer.

Key words : JESD204B；high speed serial transmission；UDP protocol；RGMII interface