中圖分類號(hào)： TN911；TP335
文獻(xiàn)標(biāo)識(shí)碼： A
DOI：10.16157/j.issn.0258-7998.200814
中文引用格式： 劉思軍，秦明偉，劉多強(qiáng). 高吞吐率低時(shí)延圖像DCT處理器設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2021，47(9)：69-74.
英文引用格式： Liu Sijun，Qin Mingwei，Liu Duoqiang. Design of high throughput rate low latency image DCT processor[J]. Application of Electronic Technique，2021，47(9)：69-74.

Design of high throughput rate low latency image DCT processor

Abstract： Aiming at the high-resolution and high-frame rate image real-time compression problem, a discrete cosine transform processor for high-speed image JPEG compression coding system was designed. The designed discrete cosine transform(DCT) processor is based on the Virtex-7 series FPGA, which makes full use of parallel and pipeline processing technology, and implements a fast two-dimensional discrete cosine transform(2D-DCT) by using a matrix-like decomposition algorithm based on the butterfly flow graph structure. In order to improve the data throughput rate, a dual-core DCT unit is designed to process 16 pixels at the same time, which improves the processing speed and reduces the delay as a whole. The board test shows that the calculation results of high-speed image DCT processor are correct. Under the 200 MHz system clock, the throughput rate is up to 3 GB/s, and the average image processing time per frame is no more than 10 ms, realizing the real-time processing of high-speed images.

Key words : image compression；discrete cosine transform(DCT)；FPGA；parallel pipeline structure；high throughput