基于Innovus的復(fù)雜時鐘結(jié)構(gòu)分析及實現(xiàn)
2020年電子技術(shù)應(yīng)用第8期
曾晉偉
深圳市中興微電子技術(shù)有限公司,四川 成都610041
摘要: 在先進工藝節(jié)點下,隨著設(shè)計規(guī)模越來越大,時鐘頻率越來越高以及時鐘結(jié)構(gòu)越來越復(fù)雜,最終整個設(shè)計收斂對于時鐘質(zhì)量的依賴越來越明顯。針對類似多輸入動態(tài)mux復(fù)雜時鐘、IP模塊多內(nèi)部輸出時鐘等復(fù)雜的時鐘結(jié)構(gòu),采用分析時鐘框圖及基于Innovus工具從網(wǎng)表中提取時鐘結(jié)構(gòu)的分析方式進行時鐘結(jié)構(gòu)上的詳細梳理,提出針對時鐘結(jié)構(gòu)分析及clock spec的優(yōu)化方法。同時在一個超大規(guī)模的16 nm top design上基于優(yōu)化后的clock spec進行CTS,并結(jié)合multi-tap的clock tree做法,從得到的結(jié)果可以發(fā)現(xiàn)在run time、clock latency等方面都有較大的提升,能夠滿足項目要求的時鐘長度等要求,有效避免block接口的時序沖突。
中圖分類號: TN402
文獻標識碼: A
DOI:10.16157/j.issn.0258-7998.209803
中文引用格式: 曾晉偉. 基于Innovus的復(fù)雜時鐘結(jié)構(gòu)分析及實現(xiàn)[J].電子技術(shù)應(yīng)用,2020,46(8):64-67.
英文引用格式: Zeng Jinwei. Complicated clock structure analysis and implementation with Innovus implementation system[J]. Application of Electronic Technique,2020,46(8):64-67.
文獻標識碼: A
DOI:10.16157/j.issn.0258-7998.209803
中文引用格式: 曾晉偉. 基于Innovus的復(fù)雜時鐘結(jié)構(gòu)分析及實現(xiàn)[J].電子技術(shù)應(yīng)用,2020,46(8):64-67.
英文引用格式: Zeng Jinwei. Complicated clock structure analysis and implementation with Innovus implementation system[J]. Application of Electronic Technique,2020,46(8):64-67.
Complicated clock structure analysis and implementation with Innovus implementation system
Zeng Jinwei
Sanechips Technology Co.,Ltd.,Chengdu 610041,China
Abstract: In advanced process node, as the design scale becomes larger and larger, the clock frequency becomes higher and the clock structure becomes more and more complicated, it is increasingly found that the closure of the design depends more and more on the clock quality. For complicated clock structures such as multi-input dynamic mux, IP modules with multiple internal output clocks, etc., the clock structure is analyzed, and the clock structure is extracted from the netlist based on the Innovus tool, clock spec will be updated based on these analysis. At the same time, CTS is performed on an ultra-large 16 nm top design based on the optimized clock spec, combined with the multi-tap clock tree methodology. From the results obtained, it can be found that the run time, clock latency and other aspects have been greatly improved. It can meet the requirements such as the clock length required by the project, and effectively avoid the timing conflict of the block interface.
Key words : Innovus;physical design;clock tree;multi-tap CTS
0 引言
隨著集成電路工藝進入先進節(jié)點(Advanced Node),以及應(yīng)用場景的不斷增加,帶來芯片設(shè)計規(guī)模越來越大以及時鐘結(jié)構(gòu)更加復(fù)雜,針對時鐘結(jié)構(gòu)的分析與時鐘的實現(xiàn)也更加困難。就時鐘樹綜合(Clock Tree Synthesis,CTS)而言,時鐘結(jié)構(gòu)復(fù)雜程度的增加,可能會帶來公共路徑(Common Path)的長度減少,片上誤差(On Chip Variation,OCV)的影響增加,CTS迭代時間(Turn-Around Time)增加,以及時鐘上功耗增加等問題。因此,在物理實現(xiàn)中,CTS變得越來越重要。
在本文中,借助于Cadence公司的自動化布局布線工具Innovus,首先探討了針對復(fù)雜時鐘結(jié)構(gòu)的時鐘如何進行分析,其次基于分析結(jié)果提出時鐘實現(xiàn)上可能出現(xiàn)的問題以及解決方案,再次,基于調(diào)整進行CTS實現(xiàn),并與傳統(tǒng)CTS方案的結(jié)果進行對比,最后對本文進行總結(jié)并對結(jié)論進行進一步分析。
本文詳細內(nèi)容請下載:http://ihrv.cn/resource/share/2000002947
作者信息:
曾晉偉
(深圳市中興微電子技術(shù)有限公司,四川 成都610041)
此內(nèi)容為AET網(wǎng)站原創(chuàng),未經(jīng)授權(quán)禁止轉(zhuǎn)載。