Altera公司的Arria GX FPGA是帶有收發(fā)器的中端FPGA系列。其收發(fā)器速率高達(dá)3.125 Gbps，您可以利用它來(lái)連接支持PCI Express,千兆以太網(wǎng),Serial RapidIO,SDI等協(xié)議的現(xiàn)有模塊和器件。具有同類最佳的信號(hào)完整性, 是功耗最低的中端FPGA，適用于需要32個(gè)支持背板的6.5536 Gbps收發(fā)器的應(yīng)用.本文介紹了Arria®GX FPGA主要特性和架構(gòu)圖,以及Arria V GX FPGA入門(mén)開(kāi)發(fā)板主要特性,框圖,電路圖,PCB元件布局圖和材料清單.

Arria®GX FPGA是Altera帶有收發(fā)器的中端FPGA系列。其收發(fā)器速率高達(dá)3.125 Gbps，您可以利用它來(lái)連接支持PCI Express、千兆以太網(wǎng)、Serial RapidIO、SDI等協(xié)議的現(xiàn)有模塊和器件。Arria GX FPGA含有Altera的第四代收發(fā)器，確保您的設(shè)計(jì)具有優(yōu)異的信號(hào)完整性。

同類最佳的信號(hào)完整性

Arria GX收發(fā)器基于最初為Stratix II GX FPGA系列開(kāi)發(fā)而大獲成功的技術(shù)之上。所有系列均采用90nm工藝技術(shù)生產(chǎn)，使用相同的物理介質(zhì)附加(PMA)電路。Arria GX還含有Stratix II GX FPGA物理編碼子層(PCS)的子集。結(jié)合倒裝焊封裝，這些特性在低成本收發(fā)器FPGA中實(shí)現(xiàn)了同類最佳的信號(hào)完整性。

獲得大獎(jiǎng)的軟件工具和IP，提高了效能

Altera的Quartus II 和SOPCBuilder幫助您迅速輕松地將設(shè)計(jì)構(gòu)思實(shí)現(xiàn)為最終產(chǎn)品。Quartus II 以最快的編譯時(shí)間和精確的結(jié)果幫助您提高效能。利用SOPCBuilder，您可以在簡(jiǎn)單直觀的圖形界面下，無(wú)縫連接知識(shí)產(chǎn)權(quán)(IP)模塊。此外，Timequest是強(qiáng)大的ASIC功能時(shí)序分析器，支持業(yè)界標(biāo)準(zhǔn)Synopsys設(shè)計(jì)約束(SDC)格式。

世界范圍內(nèi)的高速專家網(wǎng)絡(luò)

當(dāng)器件需要連接高速接口時(shí)，您可以咨詢Altera的系統(tǒng)級(jí)專家們，通過(guò)MySupport在線接觸專家，或者聯(lián)系當(dāng)?shù)氐默F(xiàn)場(chǎng)應(yīng)用工程師組。每一地區(qū)支持中心(RSC)的高速串行接口系統(tǒng)專家在MySupport上回答您提出的問(wèn)題。Altera在北美設(shè)立了RSC應(yīng)用工程師組。

The Arria® V device family consists of the most comprehensive offerings of mid-range FPGAs ranging from the lowest power for 6 gigabits per second (Gbps) and 10 Gbps applications, to the highest mid-range FPGA bandwidth 12.5 Gbps transceivers.

The Arria V devices are ideal for power-sensitive wireless infrastructure equipment, 20G/40G bridging, switching, and packet processing applications, high-definition video processing and image manipulation, and intensive digital signal processing (DSP) applications.

Arria®GX FPGA主要特性:

■ Transceiver block features
■ High-speed serial transceiver channels with CDR support up to 3.125 Gbps.
■ Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels
■ Support for the following CDR-based bus standards—PCI Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode
■ Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
■ 1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers
■ Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode)
■ Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices
■ Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial Digital Interface (SDI), and Serial RapidIO
■ 8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
■ Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array
■ Channel aligner compliant with XAUI
■ Main device features:
■ TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to 380 MHz
■ Up to 16 global clock networks with up to 32 regional clock networks per device
■ High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters
■ Up to four enhanced phase-locked loops (PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting
■ Support for numerous single-ended and differential I/O standards
■ High-speed source-synchronous differential I/O support on up to 47 channels
■ Support for source-synchronous bus standards, including SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
■ Support for high-speed external memory including DDR and DDR2 SDRAM, and SDR SDRAM
■ Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)
■ Support for remote configuration updates

圖1. Arria V FPGA體系結(jié)構(gòu)框圖

Arria V GX入門(mén)開(kāi)發(fā)板

The Arria V GX starter board provides a hardware platform for developing and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V GX FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GX designs.

One high-speed mezzanine card (HSMC) connector is available to add additional functionality via a variety of HSMCs available from Altera® and various partners.

Arria V GX入門(mén)開(kāi)發(fā)板主要特性:

■ One Arria V GX 5AGXFB3H4F35C4N FPGA in a 1152-pin FineLine BGA (FBGA) package
■ 362,000 LEs
■ 136,880 adaptive logic modules (ALMs)
■ 17,260 Kbit on-die block memory
■ 24 high-speed transceivers
■ 12 fractional phase locked loops (PLLs)
■ 2,090 18x19 multipliers
■ 544 general purpose input/output
■ 1.1-V core voltage
■ MAX® V 5M2210ZF256C4N CPLD in a 256-pin FBGA package
■ MAX II EPM570F100C5N CPLD in a 100-pin FBGA package
■ FPGA configuration circuitry
■ MAX V CPLD 5M2210ZF256C4N System Controller and flash fast passive parallel (FPP) configuration
■ On-board USB-BlasterTM II for use with the Quartus® II Programmer
■ Clocking circuitry
■ Programmable clock generator for FPGA reference clock input
■ 125-MHz LVDS oscillator for FPGA reference clock input
■ 148.5/148.35-MHz LVDS VCXO for FPGA reference clock input
■ 50-MHz single-ended oscillator for FPGA and CPLD clock input
■ 100-MHz single-ended oscillator for CPLD configuration clock input
■ SMA input (LVPECL)
■ Memory
■ Two 128-Mbyte (MB) DDR3 SDRAM with a total of 32-bit data bus
■ 2-MB SSRAM
■ Two 128-MB synchronous flash
■ General user I/O
■ LEDs and displays
■ Four user LEDs
■ One two-line character LCD display
■ Three configuration select LED
■ One configuration done LED
■ Four on-board USB-Blaster II status LEDs
■ Two HSMC interface transmit/receive LED (TX/RX)
■ Four PCI Express LEDs
■ Five Ethernet LEDs
■ One serial digital interface (SDI) carrier detect LED
■ Push buttons
■ One CPU reset push button
■ One configuration reset push button
■ Three general user push buttons
■ DIP switches
■ Four MAX V CPLD System Controller control switches
■ Three JTAG chain control switches
■ Three PCI Express link width switches
■ Four general user switches
■ Power supply
■ 19-V (laptop) DC input
■ PCI Express edge connector power
■ Mechanical
■ PCI card standard size (6.600" x 4.199")

圖2.Arria V GX入門(mén)開(kāi)發(fā)板框圖

圖3.Arria V GX入門(mén)開(kāi)發(fā)板外形圖

Arria V GX入門(mén)開(kāi)發(fā)板包括:

硬件:
• Arria V GX FPGA Starter Board running on Arria V GX 5AGXFB3H4F35C4N FPGA
• DDR3 memory
• One HSMC connector supporting LVDS and single-ended I/Os
• PCIe x8 edge connector
• High-definition multimedia interface (HDMI) output and serial digital interface (SDI) channel
• Character LCD
• Debug and loopback HSMC boards
• AC adapter power cables
• Ethernet, SMB-SMB, and USB cables
軟件:
• Design examples
- Board Update Portal design
- Board Test System (BTS) design
• Documentation
- Arria V GX Starter Kit User Guide
- Arria V GX Starter Board Reference Manual
- Board design files
• Design software*
- Quartus II software (required)
- Nios® II processor (optional)
- MegaCore® intellectual property (IP) library (optional)
- Mentor Graphics® ModelSim®-Altera software (optional)

圖3.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)框圖

圖4.Arria V GX入門(mén)開(kāi)發(fā)板電源樹(shù)圖

圖5.Arria V GX入門(mén)開(kāi)發(fā)板時(shí)鐘樹(shù)圖

圖6.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(1)

圖7.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(2)

圖8.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(3)

圖9.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(4)

圖10.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(5)

圖11.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(6)

圖12.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(7)

圖13.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(8)

圖14.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(9)

圖15.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(10)

圖16.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(11)

圖17.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(12)

圖18.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(13)

圖19.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(14)

圖20.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(15)

圖21.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(16)

圖22.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(17)

圖23.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(18)

圖24.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(19)

圖25.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(20)

圖26.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(21)

圖27.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(22)

圖28.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(23)

圖29.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(24)

圖30.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(25)

圖31.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(26)

圖32.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(27)

圖33.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(28)

圖34.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(29)

圖35.Arria V GX入門(mén)開(kāi)發(fā)板系統(tǒng)電路圖(30)

圖36.Arria V GX入門(mén)開(kāi)發(fā)PCB元件布局圖(頂層)

圖37.Arria V GX入門(mén)開(kāi)發(fā)PCB元件布局圖(底層)