中圖分類號(hào)：TN918 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.256257
中文引用格式： 衛(wèi)志剛，李鑫，高園. 基于FPGA的ZUC算法快速實(shí)現(xiàn)研究[J]. 電子技術(shù)應(yīng)用，2025，51(10)：69-73.
英文引用格式： Wei Zhigang，Li Xin，Gao Yuan. Research on fast implementation of ZUC algorithm based on FPGA[J]. Application of Electronic Technique，2025，51(10)：69-73.

Research on fast implementation of ZUC algorithm based on FPGA

Abstract： The ZUC algorithm is a commercial sequence cipher algorithm independently developed in China, which has been applied in complex scenarios such as real-time server computation and big data processing. The high-speed implementation of ZUC has important practical significance for its application promotion. Based on this, the ZUC algorithm was implemented on the FPGA hardware platform to meet the high-performance requirements of the ZUC applicable environment. By optimizing core operations such as modular multiplication and modular addition, and adopting a streamlined structure design, the ZUC algorithm was realized. The experimental results show that the data throughput of the ZUC algorithm core can reach 10.4 Gb/s. Compared with existing research results, it reduces the delay of critical paths, improves the operating frequency of the algorithm, and achieves a good balance between throughput and hardware resource consumption, providing a new solution for the high-performance implementation of the ZUC algorithm.

Key words : stream cipher；ZUC algorithm；optimal design；FPGA