中圖分類(lèi)號(hào)： TN47
文獻(xiàn)標(biāo)識(shí)碼： A
DOI：10.16157/j.issn.0258-7998.229803
中文引用格式： 張成，李晴，趙佳. 基于Cadence 3D-IC平臺(tái)的2.5D封裝Interposer設(shè)計(jì)[J].電子技術(shù)應(yīng)用，2022，48(8)：46-50，59.
英文引用格式： Zhang Cheng，Li Qing，Zhao Jia. 2.5D packaging interposer design based on Cadence 3D-IC platform[J]. Application of Electronic Technique，2022，48(8)：46-50，59.

2.5D packaging interposer design based on Cadence 3D-IC platform

Abstract： With the rise of industries such as big data, artificial intelligence and 5G, there is a huge demand for high-speed computation, high-speed interface and low-power chip solutions. Therefore, advanced packaging, which plays a significant role in the continuation of Moore′s Law, including 2.5D and 3D packaging technology, has become an important topic in the semiconductor industry. The main difference between the 2.5D advanced packaging and the traditional 2D packaging is that there is an extra layer of silicon interposer, which uses the thin metal line width and fine metal spacing capabilities of the silicon process to achieve high density interconnection. This article described a design flow implemented with Cadence 3D-IC platform by which a 2.5D packaging interposer design is developed on Globalfoundries 65nm technology process. HBM2e 3.2 Gb/s high speed interconnect on a 3-Metal-Interposer is achieved and verified by signal and power integrity simulation and analysis making this product has both performance and cost advantages.

Key words : 2.5D advanced package；Si-interposer；HBM；3D-IC