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基于PCIe Gen5的低成本Coupon設(shè)計(jì)
2022年電子技術(shù)應(yīng)用第6期
劉 濤,宗艷艷,王乾輝,秦玉倩,田民政,余華國
浪潮電子信息產(chǎn)業(yè)股份有限公司,山東 濟(jì)南250101
摘要: 數(shù)字技術(shù)發(fā)展日新月異,新一代服務(wù)器產(chǎn)品中,PCIe Gen5信號速率已經(jīng)達(dá)到32 Gb/s,為了確保其信號完整性設(shè)計(jì),單板損耗監(jiān)控必不可少,優(yōu)良的Coupon設(shè)計(jì)因此顯得尤為重要。傳統(tǒng)Coupon多采用Litek探頭技術(shù),以折線方式布線,盡管技術(shù)成熟,但存在占用空間大,數(shù)據(jù)穩(wěn)定性差等問題。從產(chǎn)品設(shè)計(jì)的低成本需求出發(fā),對PCIe Gen5信號的低成本Coupon設(shè)計(jì)展開研究,結(jié)合差分繞線理論分析以及仿真數(shù)據(jù),對幾種不同繞線方式進(jìn)行分析對比,選擇了一種低空間占有率且高可靠性的Coupon布線方式,并對測試治具進(jìn)行了改進(jìn)。實(shí)驗(yàn)結(jié)果表明,提出的Coupon設(shè)計(jì)方法不僅比傳統(tǒng)方法占用空間少,而且數(shù)據(jù)穩(wěn)定性更高,更加有利于Coupon的低成本、高可靠性設(shè)計(jì)。
中圖分類號: TN402
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.211960
中文引用格式: 劉濤,宗艷艷,王乾輝,等. 基于PCIe Gen5的低成本Coupon設(shè)計(jì)[J].電子技術(shù)應(yīng)用,2022,48(6):116-120.
英文引用格式: Liu Tao,Zong Yanyan,Wang Qianhui,et al. Low-cost Coupon design based on PCIe Gen5 signal[J]. Application of Electronic Technique,2022,48(6):116-120.
Low-cost Coupon design based on PCIe Gen5 signal
Liu Tao,Zong Yanyan,Wang Qianhui,Qin Yuqian,Tian Minzheng,Yu Huaguo
Inspur Electronic Information Industry Co.,Ltd.,Jinan 250101,China
Abstract: The development of digital technology is changing rapidly. In the new generation of server products, the PCIe Gen5 signal rate has reached 32 Gb/s. In order to ensure its signal integrity design, single-board loss monitoring is essential, and a good Coupon design is therefore particularly important. Traditional Coupons mostly use Litek probe technology, and wiring in a broken line. Although the technology is mature, there are still many problems such as large space occupation and poor data stability. Based on the low-cost requirements of product design, this paper researches on the low-cost Coupon design of PCIe Gen5 signal. Different wiring methods are analyzed and compared through theoretical analysis and simulation. Then the high-reliability Coupon wiring method is selected which can also takes up less space. The test fixture is also optimized which can also improve data stability. Experimental results show that the Coupon design method proposed in this paper not only takes up less space than traditional methods, but also has higher data stability. Therefore, this method is more conducive to the low-cost and high-reliability design of Coupons.
Key words : PCIe;32 Gb/s;Coupon;phase difference;test verification

0 引言

    互聯(lián)網(wǎng)技術(shù)飛速發(fā)展,萬物高速互連早已成為不可逆轉(zhuǎn)的發(fā)展趨勢,為了滿足日益增長的數(shù)據(jù)存儲、傳輸與交換需求,信號速率也正在以前所未有的速度進(jìn)行升級換代,以服務(wù)器系統(tǒng)中代表性的PCIe總線為例,信號經(jīng)歷了從第一代產(chǎn)品的2.5 Gb/s速率,到如今主推的第五代32 Gb/s速率,乃至即將發(fā)行的第六代64 Gb/s速率的飛速革新[1]。盡管速率提升可以有力推動數(shù)字技術(shù)發(fā)展,卻也帶來了一系列的困難和挑戰(zhàn),對于SI工程師來說,如何在高度集成的復(fù)雜電子系統(tǒng)中保證高速信號質(zhì)量,完成信號完整性設(shè)計(jì),成為了越來越突出的重難點(diǎn)問題。

    所謂信號完整性設(shè)計(jì),就是要對引起高速信號失真的各種因素進(jìn)行優(yōu)化,盡量減少信號失真,保證其能準(zhǔn)確傳遞信息。引起信號失真的因素主要包括信號網(wǎng)絡(luò)之間產(chǎn)生的串?dāng)_問題,以及信號自身傳輸媒介引起的反射和損耗問題[2]。因?yàn)閭鬏斅窂酱嬖诘刃Т?lián)和并聯(lián)電阻,信號在此媒介中傳輸時(shí)必然會有一定的能量損耗,通常高頻分量損耗比低頻分量大,導(dǎo)致了信號上升邊退化現(xiàn)象,引起符號間干擾(ISI)和眼圖塌陷等一系列問題[3]。新一代服務(wù)器產(chǎn)品中,PCIe Gen5信號速率高達(dá)32 Gb/s,損耗引起的上升邊退化問題尤為嚴(yán)重,必須進(jìn)行優(yōu)化設(shè)計(jì)。




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作者信息:

劉  濤,宗艷艷,王乾輝,秦玉倩,田民政,余華國

(浪潮電子信息產(chǎn)業(yè)股份有限公司,山東 濟(jì)南250101)




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