《電子技術(shù)應(yīng)用》
您所在的位置:首頁 > 其他 > 设计应用 > 基于PCIe Gen5的低成本Coupon设计
基于PCIe Gen5的低成本Coupon设计
2022年电子技术应用第6期
刘 涛,宗艳艳,王乾辉,秦玉倩,田民政,余华国
浪潮电子信息产业股份有限公司,山东 济南250101
摘要: 数字技术发展日新月异,新一代服务器产品中,PCIe Gen5信号速率已经达到32 Gb/s,为了确保其信号完整性设计,单板损耗监控必不可少,优良的Coupon设计因此显得尤为重要。传统Coupon多采用Litek探头技术,以折线方式布线,尽管技术成熟,但存在占用空间大,数据稳定性差等问题。从产品设计的低成本需求出发,对PCIe Gen5信号的低成本Coupon设计展开研究,结合差分绕线理论分析以及仿真数据,对几种不同绕线方式进行分析对比,选择了一种低空间占有率且高可靠性的Coupon布线方式,并对测试治具进行了改进。实验结果表明,提出的Coupon设计方法不仅比传统方法占用空间少,而且数据稳定性更高,更加有利于Coupon的低成本、高可靠性设计。
關(guān)鍵詞: PCIe 32Gbs Coupon 相位差 测试验证
中圖分類號: TN402
文獻標識碼: A
DOI:10.16157/j.issn.0258-7998.211960
中文引用格式: 劉濤,宗艷艷,王乾輝,等. 基于PCIe Gen5的低成本Coupon設(shè)計[J].電子技術(shù)應(yīng)用,2022,48(6):116-120.
英文引用格式: Liu Tao,Zong Yanyan,Wang Qianhui,et al. Low-cost Coupon design based on PCIe Gen5 signal[J]. Application of Electronic Technique,2022,48(6):116-120.
Low-cost Coupon design based on PCIe Gen5 signal
Liu Tao,Zong Yanyan,Wang Qianhui,Qin Yuqian,Tian Minzheng,Yu Huaguo
Inspur Electronic Information Industry Co.,Ltd.,Jinan 250101,China
Abstract: The development of digital technology is changing rapidly. In the new generation of server products, the PCIe Gen5 signal rate has reached 32 Gb/s. In order to ensure its signal integrity design, single-board loss monitoring is essential, and a good Coupon design is therefore particularly important. Traditional Coupons mostly use Litek probe technology, and wiring in a broken line. Although the technology is mature, there are still many problems such as large space occupation and poor data stability. Based on the low-cost requirements of product design, this paper researches on the low-cost Coupon design of PCIe Gen5 signal. Different wiring methods are analyzed and compared through theoretical analysis and simulation. Then the high-reliability Coupon wiring method is selected which can also takes up less space. The test fixture is also optimized which can also improve data stability. Experimental results show that the Coupon design method proposed in this paper not only takes up less space than traditional methods, but also has higher data stability. Therefore, this method is more conducive to the low-cost and high-reliability design of Coupons.
Key words : PCIe;32 Gb/s;Coupon;phase difference;test verification

0 引言

    互聯(lián)網(wǎng)技術(shù)飛速發(fā)展,萬物高速互連早已成為不可逆轉(zhuǎn)的發(fā)展趨勢,為了滿足日益增長的數(shù)據(jù)存儲、傳輸與交換需求,信號速率也正在以前所未有的速度進行升級換代,以服務(wù)器系統(tǒng)中代表性的PCIe總線為例,信號經(jīng)歷了從第一代產(chǎn)品的2.5 Gb/s速率,到如今主推的第五代32 Gb/s速率,乃至即將發(fā)行的第六代64 Gb/s速率的飛速革新[1]。盡管速率提升可以有力推動數(shù)字技術(shù)發(fā)展,卻也帶來了一系列的困難和挑戰(zhàn),對于SI工程師來說,如何在高度集成的復(fù)雜電子系統(tǒng)中保證高速信號質(zhì)量,完成信號完整性設(shè)計,成為了越來越突出的重難點問題。

    所謂信號完整性設(shè)計,就是要對引起高速信號失真的各種因素進行優(yōu)化,盡量減少信號失真,保證其能準確傳遞信息。引起信號失真的因素主要包括信號網(wǎng)絡(luò)之間產(chǎn)生的串擾問題,以及信號自身傳輸媒介引起的反射和損耗問題[2]。因為傳輸路徑存在等效串聯(lián)和并聯(lián)電阻,信號在此媒介中傳輸時必然會有一定的能量損耗,通常高頻分量損耗比低頻分量大,導(dǎo)致了信號上升邊退化現(xiàn)象,引起符號間干擾(ISI)和眼圖塌陷等一系列問題[3]。新一代服務(wù)器產(chǎn)品中,PCIe Gen5信號速率高達32 Gb/s,損耗引起的上升邊退化問題尤為嚴重,必須進行優(yōu)化設(shè)計。




本文詳細內(nèi)容請下載:http://ihrv.cn/resource/share/2000004433




作者信息:

劉  濤,宗艷艷,王乾輝,秦玉倩,田民政,余華國

(浪潮電子信息產(chǎn)業(yè)股份有限公司,山東 濟南250101)




wd.jpg

此內(nèi)容為AET網(wǎng)站原創(chuàng),未經(jīng)授權(quán)禁止轉(zhuǎn)載。

相關(guān)內(nèi)容