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一種PCIe轉(zhuǎn)RapidIO擴(kuò)展卡設(shè)計(jì)與實(shí)現(xiàn)
電子技術(shù)應(yīng)用
張恒,王琪,郁文君
中國(guó)電子科技集團(tuán)公司第五十八研究所
摘要: RapidIO總線是一種廣泛應(yīng)用于嵌入式系統(tǒng)內(nèi)部互聯(lián)的高性能互聯(lián)總線,具有高帶寬、低延遲、支持多處理器等特征。針對(duì)目前市面上大多數(shù)處理器不支持RapidIO 總線的問(wèn)題,基于國(guó)產(chǎn)PCIe轉(zhuǎn)RapidIO控制器設(shè)計(jì)了一款PCIe擴(kuò)展卡,詳細(xì)介紹了該P(yáng)CIe擴(kuò)展卡各模塊硬件設(shè)計(jì)方案,并搭建測(cè)試環(huán)境對(duì)RapidIO總線的眼圖和DMA傳輸性能進(jìn)行測(cè)試。經(jīng)測(cè)試,當(dāng)RapidIO總線傳輸速率配置為5 Gb/s時(shí),RapidIO總線DMA讀寫速率分別為1 677 MB/s 和1 711 MB/s。
中圖分類號(hào):TN92 文獻(xiàn)標(biāo)志碼:A DOI: 10.16157/j.issn.0258-7998.245160
中文引用格式: 張恒,王琪,郁文君. 一種PCIe轉(zhuǎn)RapidIO擴(kuò)展卡設(shè)計(jì)與實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用,2024,50(10):110-114.
英文引用格式: Zhang Heng,Wang Qi,Yu Wenjun. Design and implementation of a PCIe-to-RapidIO add-in card[J]. Application of Electronic Technique,2024,50(10):110-114.
Design and implementation of a PCIe-to-RapidIO add-in card
Zhang Heng,Wang Qi,Yu Wenjun
The 58th Research Institute of China Electronics Technology Group
Abstract: RapidIO bus is a high-performance interconnect bus which is widely used in embedded systems. It has the characteristics of high bandwidth, low latency, and multiple processors supported. In response to the problem that most processors on the market currently don’t support the RapidIO bus, a PCIe add-in card based on domestic PCIe to RapidIO controller was designed. The hardware design of each module of the PCIe add-in card was introduced in detail, and a testing environment was built to test the eye diagram and DMA transmission rate of the RapidIO bus. By testing, when the transfer rate of the RapidIO bus is configured as 5 Gb/s, the DMA read and DMA write rates of the RapidIO bus are 1 677 MB/s and 1 711 MB/s, respectively.
Key words : RapidIO bus;PCIe;PCIe to RapidIO controller;eye diagram;DMA transmission

引言

隨著嵌入式系統(tǒng)的不斷發(fā)展,芯片到芯片、板卡到板卡之間的互連對(duì)帶寬、成本、靈活性及可靠性的要求越來(lái)越高。嵌入式系統(tǒng)目前常用的互連方式主要有千兆以太網(wǎng)互連、外圍組件互連高速(Peripheral Component Interconnect express,PCIe)總線互連和快速輸入輸出(Rapid Input Output,RapidIO)總線互連。其中千兆以太網(wǎng)互連存在延時(shí)大、軟件協(xié)議開(kāi)銷大和帶寬不足等缺點(diǎn);而PCIe總線是采用主從模式的樹(shù)形拓?fù)洌恢С侄嘣O(shè)備間數(shù)據(jù)交換,更適合組建平行通信網(wǎng)絡(luò)。RapidIO總線是由Motorola和Mercury等公司提出的一種滿足高性能嵌入式系統(tǒng)需求的開(kāi)放式互連技術(shù)標(biāo)準(zhǔn),具有高帶寬、低延遲、支持多處理器等特征,比千兆以太網(wǎng)能提供更高的傳輸速率,比PCIe總線更適合組建平行通信網(wǎng)絡(luò),具有更強(qiáng)的互聯(lián)性和兼容性。RapidIO總線具有硬件重傳機(jī)制,同時(shí)支持直接內(nèi)存訪問(wèn)(Direct Memory Access,DMA) Doorbell和Message操作等,可用于點(diǎn)對(duì)點(diǎn)互連,也可采用交叉交換的拓?fù)浣Y(jié)構(gòu)實(shí)現(xiàn)多設(shè)備間的數(shù)據(jù)交換[1-9]。

鑒于目前市面上大部分處理器不支持RapidIO 總線[10-11],本文以國(guó)產(chǎn)PCIe轉(zhuǎn)RapidIO控制器為核心,設(shè)計(jì)了一種PCIe轉(zhuǎn)RapidIO擴(kuò)展卡,通過(guò)該擴(kuò)展卡可以把不支持RapidIO 總線的處理器通過(guò)RapidIO網(wǎng)絡(luò)集群到一起,組成一個(gè)強(qiáng)大的分布式計(jì)算機(jī)系統(tǒng)。


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作者信息:

張恒,王琪,郁文君

(中國(guó)電子科技集團(tuán)公司第五十八研究所,江蘇 無(wú)錫 214072)


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