中圖分類號(hào)： TN492 文獻(xiàn)標(biāo)識(shí)碼： A DOI：10.16157/j.issn.0258-7998.212214 中文引用格式： 王莞，魏敬和，于宗光. 基于BCH糾錯(cuò)算法的編解碼器設(shè)計(jì)與實(shí)現(xiàn)[J].電子技術(shù)應(yīng)用，2022，48(5)：42-46. 英文引用格式： Wang Guan，Wei Jinghe，Yu Zongguang. Design and implementation of codec based on BCH error correction algorithm[J]. Application of Electronic Technique，2022，48(5)：42-46.
Design and implementation of codec based on BCH error correction algorithm
Wang Guan1，2，Wei Jinghe1，2，Yu Zongguang1，2
1.School of IoT Engineering，Jiangnan University，Wuxi 214122，China； 2.China Electronics Technology Group Corporation No.58 Research Institute，Wuxi 214072，China
Abstract： With the rapid development of NAND Flash memory cells and the increase in storage density, the error probability of devices has increased. For this reason, an optimized BCH codec structure is proposed. The encoding and decoding process can process 16-bit data in parallel in each clock cycle. Among them, the syndrome module, error location polynomial module and Chien search module in the decoding circuit adopt a three-stage pipeline structure, and the error correction and error detection stages can be carried out at the same time, which effectively improves the data processing speed and error correction speed. After completing the RTL design of the circuit, the simulation verification of the circuit was completed by using the VCS tool. The results showed that 48-bit error correction was achieved when 8 192 bit data was transmitted to generate 672 check factors, and the maximum operating frequency was 200 MHz.
Key words : nand flash；BCH code；Chien search；pipeline structure；codec
