中圖分類號(hào)： TN709
文獻(xiàn)標(biāo)識(shí)碼： A
DOI：10.16157/j.issn.0258-7998.222673
中文引用格式： 成章，蔡春霞，江威，等. 采樣時(shí)鐘保持模式對(duì)數(shù)字接收機(jī)的影響分析[J].電子技術(shù)應(yīng)用，2022，48(10)：130-143，149.
英文引用格式： Cheng Zhang，Cai Chunxia，Jiang Wei，et al. Analysis about influences of holding mode of sample clock on digital receiver[J]. Application of Electronic Technique，2022，48(10)：130-143，149.

Analysis about influences of holding mode of sample clock on digital receiver

Abstract： In the paper, the influences of the first-level phase-locked loop on the frequency of output sample clock when entering the frequency-holding mode after losing lock in the multichannel digital receiver which adopts the double phase-locked loop to provide the sample clock are analyzed, and then the influences on the amplitude, frequency and phase parameter measurement of the multichannel digital receiver are analyzed further, and the effective redemption is conducted through the correction algorithm to achieve the parameter measurement and decoupling of sample frequency deviation, as emulation and engineering verification have proven the effectiveness of measures so that their popularization and applications are available.

Key words : sample clock; frequency-holding mode; digital receiver; spectrum correction