基于HITOC DK與3DIC Integrity的3DIC芯片物理設(shè)計
2022年電子技術(shù)應(yīng)用第8期
徐 睿,王貽源
芯盟科技,上海200000
摘要: 使用了Cadence 3DIC Integrity工具,并結(jié)合芯盟特有的HITOC(Heterogeneous Integration Technology On Chip) Design Kit,進(jìn)行了3DIC(3D異構(gòu)集成)邏輯堆疊邏輯類型芯片的后端實現(xiàn)。項目中對于Cadence 3DIC Integrity工具中的proto seeds(即最小分布單元)進(jìn)行了拆分、分布、定義等方面的研究優(yōu)化;并且對于頂層電源規(guī)劃與Hybrid Bonding bump間的布線排列進(jìn)行了算法優(yōu)化,在不影響電源網(wǎng)絡(luò)強(qiáng)壯性的情況下盡可能多地獲得Hybrid Bonding bump數(shù)量,從而增加了top die與bottom die間的端口數(shù)。最終結(jié)果顯示,在與傳統(tǒng)2D芯片實現(xiàn)的PPA(性能、功耗、面積)對比中,本實驗獲得了頻率提升12%、面積減少11.2%、功耗減少2.5%的收益。
中圖分類號: TN402
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.229805
中文引用格式: 徐睿,王貽源. 基于HITOC DK與3DIC Integrity的3DIC芯片物理設(shè)計[J].電子技術(shù)應(yīng)用,2022,48(8):55-59.
英文引用格式: Xu Rui,Wang Yiyuan. 3DIC physical design of chips based on HITOC DK and 3DIC Integrity technology[J]. Application of Electronic Technique,2022,48(8):55-59.
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.229805
中文引用格式: 徐睿,王貽源. 基于HITOC DK與3DIC Integrity的3DIC芯片物理設(shè)計[J].電子技術(shù)應(yīng)用,2022,48(8):55-59.
英文引用格式: Xu Rui,Wang Yiyuan. 3DIC physical design of chips based on HITOC DK and 3DIC Integrity technology[J]. Application of Electronic Technique,2022,48(8):55-59.
3DIC physical design of chips based on HITOC DK and 3DIC Integrity technology
Xu Rui,Wang Yiyuan
ICLEAGUE,Shanghai 200000,China
Abstract: In this paper, Cadence 3DIC Integrity and ICLEAGUE HITOC Design Kit are used to implement the back-end of 3DIC logic stack logic chip. In the project, the separation, distribution, definition and other aspects of proto seeds(i.e., minimum distribution unit) in Cadence 3DIC Integrity were studied and optimized. In addition, the paper provided an algorithm of routing arrangement between the top-level power planning and Hybrid Bonding bump,which is optimized to obtain as many Hybrid Bonding bumps as possible and also keep the strength of the power network, thus increasing the number of ports between top die and bottom die. The final results of this paper show that compared with PPA(performance, power consumption and area)implemented by traditional 2D chips, the experiment has achieved 12% increase in frequency, 11.2% reduction in area and 2.5% reduction in power consumption.
Key words : 3DIC;logic stack logic;Hybrid Bonding;HITOC Design Kit;PPA
0 引言
1956年,英特爾創(chuàng)始人戈登·摩爾提出,當(dāng)價格不變時,集成電路上可容納的元器件的數(shù)目,約每隔18~24個月便會增加一倍,性能也將提升一倍。這一定律揭示了信息技術(shù)進(jìn)步的速度。過去的半個多世紀(jì),半導(dǎo)體行業(yè)一直遵循著摩爾定律(Moore′s law)高速地發(fā)展,如今,制程節(jié)點已經(jīng)來到了5 nm,借助于EUV光刻及FINFET等先進(jìn)技術(shù),正在向3 nm甚至更先進(jìn)的節(jié)點演進(jìn)。然而,隨著芯片制造工藝不斷接近物理極限,單純的半導(dǎo)體工藝升級帶來的計算性能的提升不再像以前那么迅速,芯片發(fā)展逐漸步入后摩爾時代。3D堆疊技術(shù)是把不同功能的芯片或結(jié)構(gòu),通過堆疊技術(shù)或過孔互連等微機(jī)械加工技術(shù),使其在z軸方向上形成立體集成、信號連通,是以晶片級、芯片級等封裝和可靠性技術(shù)為目標(biāo)的三維立體堆疊加工技術(shù)。3DIC 將不同工藝制程、不同性質(zhì)的芯片整合在一個封裝體內(nèi),提供了性能、功耗、面積和成本方面的優(yōu)勢。3DIC能夠為5G芯片、CPU、車載芯片等應(yīng)用場景提供更高水平的集成、更高性能的計算和更大的通信帶寬。3DIC已經(jīng)成為后摩爾時代延續(xù)摩爾定律的最佳途徑之一。
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作者信息:
徐 睿,王貽源
(芯盟科技,上海200000)
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