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基于浮柵器件的低位寬卷積神經(jīng)網(wǎng)絡研究
信息技術與網(wǎng)絡安全
陳雅倩,黃 魯
(中國科學技術大學 微電子學院,安徽 合肥230026)
摘要: 浮柵器件(Flash)能夠?qū)⒋鎯陀嬎愕奶匦韵嘟Y合,實現(xiàn)存算一體化,但是單個浮柵單元最多只能存儲位寬為4 bit的數(shù)據(jù)。面向Nor Flash,研究了卷積神經(jīng)網(wǎng)絡參數(shù)的低位寬量化,對經(jīng)典的AlexNet、VGGNet以及ResNet通過量化感知訓練。采用非對稱量化,將模型參數(shù)從32位浮點數(shù)量化至4位定點數(shù),模型大小變?yōu)樵瓉淼?/8,針對Cifar10數(shù)據(jù)集,4位量化模型的準確率相對于全精度網(wǎng)絡僅下降不到2%。最后將量化完成的卷積神經(jīng)網(wǎng)絡模型使用Nor Flash陣列加速。Hspice仿真結果表明,相對于全精度模型,部署在Nor Flash陣列中的量化模型精度僅下降2.25%,驗證了卷積神經(jīng)網(wǎng)絡部署在Nor Flash上的可行性。
中圖分類號: TP183
文獻標識碼: A
DOI: 10.19358/j.issn.2096-5133.2021.06.007
引用格式: 陳雅倩,黃魯. 基于浮柵器件的低位寬卷積神經(jīng)網(wǎng)絡研究[J].信息技術與網(wǎng)絡安全,2021,40(6):38-42.
Quantification research of convolutional neural network oriented Nor Flash
Chen Yaqian,Huang Lu
(School of Microelectronics,University of Science and Technology of China,Hefei 230026,China)
Abstract: Flash is one of the most promising candidates to bulid processing-in-memory(PIM)structures. However,the data width in one flash is 4bit at most. This article is oriented to Nor Flash and studies the quantitzation of convolution neural network. It performs quantitative perception training on the classic AlexNet, VGGNet and ResNet, and uses asymmetric quantization to quantify the model parameters from 32-bit floating point to 4-bit, and the model size becomes 1/8 of the original. For the Cifar10 data set, the accuracy of the 4-bit quantization model is only less than 2% lower than that of the full-precision network. Finally, the quantized convolutional neural network model is accelerated by the Nor Flash array. Hspice simulation results show that the accuracy of the quantized model bulided in the Nor Flash array is only reduced by 2.25% compared to the full-precision model. The feasibility of deploying the convolutional neural network on Nor Flash is verified.
Key words : convolution neural network;quantification;computation in memory;Nor Flash

0 引言

卷積神經(jīng)網(wǎng)絡(Convolution Neural Network,CNN)在圖像識別等領域有著廣泛的應用,隨著網(wǎng)絡深度的不斷增加,CNN模型的參數(shù)也越來越多,例如Alexnet[1]網(wǎng)絡,結構為5層卷積層,3層全連接層,網(wǎng)絡參數(shù)超過5 000萬,全精度的模型需要250 MB的存儲空間,而功能更加強大的VGG[2]網(wǎng)絡和Res[3]網(wǎng)絡的深度以及參數(shù)量更是遠遠超過Alexnet。對于這些卷積神經(jīng)網(wǎng)絡,每個運算周期都需要對數(shù)百萬個參數(shù)進行讀取和運算,大量參數(shù)的讀取既影響網(wǎng)絡的計算速度也帶來了功耗問題。基于馮諾依曼架構的硬件由于計算單元和存儲單元分離,在部署CNN模型時面臨存儲墻問題,數(shù)據(jù)頻繁搬運消耗的時間和能量遠遠大于計算單元計算消耗的時間和能量。

存算一體架構的硬件相對于馮諾依曼架構的硬件,將計算單元和存儲單元合并,大大減少了數(shù)據(jù)的傳輸,從而降低功耗和加快計算速度[4],因此將深度卷積神經(jīng)網(wǎng)絡部署在基于存算一體架構的硬件上具有廣闊的前景。目前實現(xiàn)存算一體化的硬件主要包括相變存儲器[5](Phase Change Memory,PCM),阻變存儲器ReRAM[6]以及浮柵器件Flash,其中Flash由于制造工藝成熟,受到廣泛關注。



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作者信息:

陳雅倩,黃  魯

(中國科學技術大學 微電子學院,安徽 合肥230026)


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