Lattice公司的LPTM10-12107是平臺管理器,內(nèi)部有48個宏單元CPLD,集成了板電源管理如熱插拔,加電順序,監(jiān)測,復(fù)位產(chǎn)生,調(diào)整和富余度)以及數(shù)字板管理工能如復(fù)位子系統(tǒng),非易失性誤差記錄,無縫邏輯,板數(shù)字信號監(jiān)測和控制,系統(tǒng)總線接口等),提供12個單獨模擬輸入通路,監(jiān)測多達(dá)12個電源測試點,每個電源輸出電壓采用數(shù)字閉環(huán)控制模式,在各種負(fù)載條件下誤差0.5%內(nèi).本文介紹了Lattice平臺管理器主要特性,方框圖,典型應(yīng)用以及Lattice平臺管理器開發(fā)套件主要特性,電路圖和材料清單.

The Lattice Platform Manager integrates board power management (hot-swap, sequencing, monitoring, reset generation, trimming and margining) and digital board management functions (reset tree, non-volatile error logging, glue logic, board digital signal monitoring and control, system bus interface, etc.) into a single integrated solution. The Platform Manager device provides 12 independent analog input channels to monitor up to 12 power supply test points. Up to 12 of these input channels can be monitored through differential inputs to support remote ground sensing. Each of the analog input channels is monitored through two independently programmable comparators to support both high/low and in-bounds/ out-of-bounds (window-compare) monitor functions. Up to six general purpose 5V tolerant digital inputs are also provided for miscellaneous control functions. There are 16 open-drain digital outputs that can be used for controlling DC-DC converters, low-drop-out regulators (LDOs) and opto-couplers, as well as for supervisory and general purpose logic interface functions. Four of these outputs (HVOUT1-HVOUT4) may be configured as high-voltage MOSFET drivers. In highvoltage mode these outputs can provide up to 12V for driving the gates of n-channel MOSFETs so that they can be used as high-side power switches controlling the supplies with a programmable ramp rate for both ramp up and ramp down.

Lattice平臺管理器主要特性:

?Precision Voltage Monitoring Increases Reliability

• 12 independent analog monitor inputs

• Differential inputs for remote ground sense

• Two programmable threshold comparators per analog input

• Hardware window comparison

• 10-bit ADC for I2C monitoring

? High-Voltage FET Drivers Enable Integration

• Power supply ramp up/down control

• Programmable current and voltage output

• Independently configurable for FET control or digital output

? Power Supply Margin and Trim Functions

• Trim and margin up to eight power supplies

• Dynamic voltage control through I2C

• Independent Digital Closed-Loop Trim function for each output

? Programmable Timers Increase Control Flexibility

• Four independent timers

• 32 us to 2 second intervals for timing sequences

? PLD Resources Integrate Power and Digital Functions

• 48-macrocell CPLD

• 640 LUT4s FPGA

• Up to 107 digital I/Os

• Up to 6.1 Kbits distributed RAM

? Programmable sysIO™ Buffer Supports a Range of Interfaces

• LVCMOS 3.3/2.5/1.8/1.5/1.2

• LVTTL

? System-Level Support

• Single 3.3V supply operation

• Industrial temperature range: -40°C to +85°C

? In-System Programmability Reduces Risk

• Integrated non-volatile configuration memory

• JTAG programming interface

? Package Options

• 128-pin TQFP

• 208-ball ftBGA

• RoHS compliant and halogen-free

圖1.Lattice平臺管理器方框圖

The board power management function can be implemented using an internal 48-macrocell CPLD. The status of all of the comparators on the analog input channels as well as the general purpose digital inputs are used as inputs by the CPLD array, and all digital outputs (open-drain as well as HVOUT) may be controlled by the CPLD. Four independently programmable timers can create delays and time-outs ranging from 32 ?s to 2 seconds. The Platform Manager device incorporates up to eight DACs for generating trimming voltage to control the output voltage of a DC-DC converter. Additionally, each power supply output voltage can be maintained typically within 0.5% tolerance across various load conditions using the Digital Closed Loop Control mode. The internal 10-bit A/D converter can both be used to monitor the VMON voltage through the I2C bus as well as for implementing digital closed loop mode for maintaining the output voltage of all power supplies controlled by the monitoring and trimming section of the Platform Manager device. The FPGA section of the Platform Manager is optimized to meet the requirements of board management functions including reset distribution, boundary scan management, fault logging, FPGA load control, and system bus inter-face. The FPGA section uses look-up tables (LUTs) and distributed memories for flexible and efficient logic imple-mentation. This instant-on capability enables the Platform Manager devices to integrate control functions that are required as soon as power is applied to the board. Power management functions can be integrated into the CPLD and digital board management functions can be integrated into the FPGA using the LogiBuilder tool provided by PAC-Designer®software. In addition, the FPGA designs can also be implemented in VHDL or Verilog HDL through the ispLEVER®software design tool. The Platform Manager IC supports a hardware I2C/SMBus slave interface that can be used to measure voltages through the Analog to Digital Converter or is used for trimming and margining using a microcontroller. There are two JTAG ports integrated into the Platform Manager device: Power JTAG and FPGA JTAG. The Power JTAG interface is used to program the power section of the Platform Manager and the FPGA JTAG is used to con-figure the FPGA portion of the device. The FPGA configuration memory can be changed in-system without inter-rupting the operation of the board management section. However, the Power Management section of the platform Manager cannot be changed without interrupting the power management operation.

Lattice平臺管理器系列選型表:

Lattice平臺管理器功能:

Detect Faults Across 12 Supplies

Margin and Trim up to 8 Supplies

Capture and Log Faults to Non-Volatile Memory

4 Hot-Swap Controllers

Flexible Reset Distribution

Configuration of Payload ICs at Power-on

Voltage Scaling / VID Control

Fan Control


圖2.Lattice平臺管理器典型應(yīng)用

Lattice平臺管理器開發(fā)套件

This user’s guide describes how to start using the Platform Manager Development Kit, an easy-to-use system for evaluating and designing with the Platform Manager mixed-signal device. The kit serves as a development test environment to build designs for power supply man-agement functions such as sequencing, power supply fault logging, trimming, reset generation, high-side MOSFET drive and user logic I/O expansion in an FPGA.

Lattice平臺管理器開發(fā)套件包括:

• Platform Manager Evaluation Board containing the Platform Manager LPTM10-12107 device in a 208-ball ftBGA package

• USB programming support on-board

• 4Mbit SPI Flash memory for logging data and faults

• SPI and I2C interfaces

• 2x16 expansion header for I2C, SPI and general purpose data bus, I/O

• Two 4-bit DIP switches

• Three push-buttons for input control, reset, etc.

• DAC and A/D convertors for trimming power supplies

• LED displays

• LCD display

• Adjustable potentiometers for user faults or demos

• Thermistor circuit for temperature sensing

• LDO to demo sequencing and trim functions

• DC-DC convertor to demo sequencing and trim functions

• Two LDOs for main chip power and VCCIO supplies.

• VMON, voltage monitors for on-board and off-board power supply monitoring

• Off-board screw connectors for user loads and testing

• Prototyping/interface connections

• Pre-loaded Demo – The Platform Manager Development Kit contains a pre-loaded demo design that illustrates many of the key features of the Platform Manager device.

• USB Connector Cable – The Platform Manager Evaluation Board is programmed via the USB cable driven from the user’s computer. This USB cable is included in the Platform Manager Development Kit.

• Power Supply – The Platform Manager Evaluation board is powered by an AC adapter (included).

圖3.Lattice平臺管理器評估板外形圖

圖4.Lattice平臺管理器評估板電路圖:復(fù)接器

圖5.Lattice平臺管理器評估板電路圖:Bank0, Bank3

圖6.Lattice平臺管理器評估板電路圖:LPTM10-12107-DEC-EVN

圖7.Lattice平臺管理器評估板電路圖:插座Logo

圖8.Lattice平臺管理器評估板電路圖:JTAG 鏈

圖9.Lattice平臺管理器評估板電路圖:LCD Bank 3

圖10.Lattice平臺管理器評估板電路圖:LED

圖11.Lattice平臺管理器評估板電路圖:CPLD輸出

圖12.Lattice平臺管理器評估板電路圖:USB
 
圖13.Lattice平臺管理器評估板電路圖:板電源

圖14.Lattice平臺管理器評估板電路圖:用戶電源

圖15.Lattice平臺管理器評估板電路圖:SPI閃存風(fēng)扇盤

圖16.Lattice平臺管理器評估板電路圖:DIP開關(guān)

圖17.Lattice平臺管理器評估板電路圖:VMON, DAC, 滑動電位計
Lattice平臺管理器評估板材料清單:



詳情請見:
http://www.latticesemi.com/documents/DS1036.pdf
和
http://www.latticesemi.com/documents/EB58.pdf