ADI公司的AD9253是集成了取樣保持電路的四路14位125MSPS模數(shù)轉(zhuǎn)換器(ADC),具有低成本,低功耗,體積小和容易使用的特點(diǎn),工作電壓1.8V,125MSPS速率時(shí)每路功耗為110mW,SNR = 74 dB ,SFDR = 90 dBc和DNL = ±0.75 LSB,滿功率模擬帶寬650MHz,可編程輸出分辨率,主要用在超聲波圖像儀,高速取樣,正交和多功能無線電接收器以及測試設(shè)備.本文介紹了AD9253產(chǎn)品亮點(diǎn)和主要特性,功能框圖,以及AD9253CE01A評(píng)估板主要特性,電路圖和材料清單.
The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample- and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.
The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
The AD9253 is available in a RoHS-compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40℃ to +85℃. This product is protected by a U.S. patent.
AD9253產(chǎn)品亮點(diǎn):
Small Footprint. Four ADCs are contained in a small, space-saving package.
Low power of 110 mW/channel at 125 MSPS with scalable power options.
Pin compatible to the AD9633 12-bit quad ADC.
Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation.
User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements.
AD9253主要特性:
1.8 V supply operation
Low power: 110 mW per channel at 125 MSPS with scalable power options
SNR = 74 dB (to Nyquist)
SFDR = 90 dBc (to Nyquist)
DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical)
Serial LVDS (ANSI-644, default) and low power, reduced signal option (similar to IEEE 1596.3)
650 MHz full power analog bandwidth
2 V p-p input voltage range
Serial port control
Full chip and individual channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Multichip sync and clock divider
Programmable output clock and data alignment
Programmable output resolution
Standby mode
AD9253應(yīng)用:
Medical ultrasound
High speed imaging
Quadrature radio receivers
Diversity radio receivers
Test equipment
圖1. AD9253功能框圖
AD9253CE01A評(píng)估板
The AD9253CE01A is an evaluation board for the AD9253-125 and the AD9633-125, quad 14 and 12-bit ADCs. This reference design provides all of the support circuitry required to operate the devices in their various modes and configurations. It is designed to interface directly with the HSC-ADC-EVALC data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI Controller software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD9253 and AD9633. User guide UG-328 provides documentation and instructions to configure the device for performance evaluation in the lab. (WIKI Site)
The AD9253 and AD9633 data sheets provide additional information related to device configuration and performance, and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page.
圖2.AD9253CE01A評(píng)估板外形圖
AD9253CE01A評(píng)估板主要特性:
Full featured evaluation board for the AD9253/AD9633
SPI interface for setup and control
External, on-board oscillator, or AD9517 clocking option
Balun/transformer or amplifier input drive option
On-board LDO regulator needing a single external 6 V, 2 A dc supply
VisualAnalog® and SPI controller software interfaces
圖3.AD9253CE01A評(píng)估板電路圖(1)
圖4.AD9253CE01A評(píng)估板電路圖(2)
圖5.AD9253CE01A評(píng)估板電路圖(3)
圖6.AD9253CE01A評(píng)估板電路圖(4)
圖7.AD9253CE01A評(píng)估板電路圖(5)
圖8.AD9253CE01A評(píng)估板電路圖(6)
圖9.AD9253CE01A評(píng)估板電路圖(7)
圖10.AD9253CE01A評(píng)估板電路圖(8)
圖11.AD9253CE01A評(píng)估板電路圖(9)
圖12.AD9253CE01A評(píng)估板電路圖(10)
AD9253CE01A評(píng)估板材料清單見:
AD9253CE01A評(píng)估板材料清單.xls
詳情請(qǐng)見:
http://www.analog.com/static/imported-files/data_sheets/AD9253.pdf
