Altera公司的Stratix IV 40nm FPGA包括Stratix IV E, Stratix IV GX和Stratix IV GT三個(gè)系列, 具有最高的密度(680K 邏輯單元(LE),22.4 Mbits 嵌入式存儲(chǔ)器和1,360個(gè)18 x 18 乘法器),最佳的性能以及最低的功耗, 系統(tǒng)帶寬(8.5 Gbps的48 個(gè)高速收發(fā)器，以及 1,067 Mbps (533 MHz) DDR3存儲(chǔ)器接口)達(dá)到了前所未有的水平，并具有優(yōu)異的信號(hào)完整性, 非常適合無線通信,固網(wǎng),軍事,廣播等其他最終市場(chǎng)中的高端數(shù)字應(yīng)用。本文介紹了Stratix® IV FPGA主要特性, Stratix IV GT器件框圖,以及采用EP4S100G5F45I1 Stratix IV GT FPGA器件的Stratix IV GT 100G開發(fā)板主要特性,方框圖,詳細(xì)電路圖和材料清單.

Altera® Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40-nm process technology and surpass all other high-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements.

The Stratix IV device family contains three optimized variants to meet different application requirements:

■ Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits
(Kb) RAM, and 1,288 18 x 18 bit multipliers

■ Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-based transceivers at up to 8.5 Gbps

■ Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers, and 48 full-duplex CDR-based transceivers at up to 11.3 Gbps

Stratix® IV FPGA主要特性:

The following list summarizes the Stratix IV device family features:

■ Up to 48 full-duplex CDR-based transceivers in Stratix IV GX and GT devices supporting data rates up to 8.5 Gbps and 11.3 Gbps, respectively

■ Dedicated circuitry to support physical layer functionality for popular serial protocols, such as PCI Express (PCIe) (PIPE) Gen1 and Gen2, Gbps Ethernet (GbE), Serial RapidIO, SONET/SDH, XAUI/HiGig, (OIF) CEI-6G, SD/HD/3G-SDI, Fibre Channel, SFI-5, and Interlaken

■ Complete PCIe protocol solution with embedded PCIe hard IP blocks that implement PHY-MAC layer, Data Link layer, and Transaction layer functionality

■ Programmable transmitter pre-emphasis and receiver equalization circuitry to compensate for frequency-dependent losses in the physical medium

■ Typical physical medium attachment (PMA) power consumption of 100 mW at 3.125 Gbps and 135 mW at 6.375 Gbps per channel

■ 72,600 to 813,050 equivalent LEs per device

■ 7,370 to 33,294 Kb of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and FIFO buffers

■ High-speed digital signal processing (DSP) blocks configurable as 9 x 9-bit, 12 x 12-bit, 18 x 18-bit, and 36 x 36-bit full-precision multipliers at up to 600 MHz

■ Up to 16 global clocks (GCLK), 88 regional clocks (RCLK), and 132 periphery clocks (PCLK) per device

■ Programmable power technology that minimizes power while maximizing device performance

■ Up to 1,120 user I/O pins arranged in 24 modular I/O banks that support a wide range of single-ended and differential I/O standards

■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks

■ High-speed LVDS I/O support with serializer/deserializer (SERDES), dynamic phase alignment (DPA), and soft-CDR circuitry at data rates up to 1.6 Gbps

■ Support for source-synchronous bus standards, including SGMII, GbE, SPI-4 Phase 2 (POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1

■ Pinouts for Stratix IV E devices designed to allow migration of designs from Stratix III to Stratix IV E with minimal PCB impact

Stratix IV GT Devices

Stratix IV GT devices provide up to 48 CDR-based transceiver channels per device:

■ Thirty-two out of the 48 transceiver channels have dedicated PCS and PMA circuitry and support data rates between 600 Mbps and 11.3 Gbps

■ The remaining 16 transceiver channels have dedicated PMA-only circuitry and support data rates between 600 Mbps and 6.5 Gbps

圖1. Stratix IV GT器件框圖
Stratix IV GT器件主要特性:


采用EP4S100G5F45I1 Stratix IV GT FPGA器件的Stratix IV GT 100G開發(fā)板
Stratix IV GT 器件EP4S100G5F45I1主要特性:


The Stratix IV GT 100G development board provides a hardware platform for evaluating the performance and signal integrity features of the Altera® Stratix IV GT devices.

Altera的Stratix^® IV GT版100G開發(fā)套件支持您對(duì)100GbE設(shè)計(jì)進(jìn)行全面評(píng)估：

通過光模塊，支持10G/40G和100G線路接口。

通過4x18 ADRII和4x32 DDR3存儲(chǔ)器塊，支持需要外部存儲(chǔ)器接口的應(yīng)用。

通過兩對(duì)FCI AirMax連接器，使用系統(tǒng)側(cè)接口。

全面的線路側(cè)(光模塊)至系統(tǒng)側(cè)(AirMax連接器)數(shù)據(jù)通路分析。

評(píng)估性能高達(dá)11.3 Gbps的收發(fā)器。

驗(yàn)證兼容10G/40G/100G以太網(wǎng)、Interlaken、CEI-6G/11G、PCI Express (Gen1, Gen2和Gen3)、Serial RapidIO^®以及其他主要標(biāo)準(zhǔn)的物理介質(zhì)附加(PMA)子層。

驗(yàn)證SFP、SFP+、QSFP和CFP等光模塊之間的互操作性。

Stratix IV GT版100G開發(fā)套件包括：

Stratix IV GT開發(fā)板(參見圖1)

安裝的器件：EP4S100G5F45I1N

EPM2210F324C3N，MAX^® II 256引腳CPLD

配置狀態(tài)和設(shè)置單元

快速被動(dòng)并行(FPP)配置

嵌入式USB-BlasterTM下載電纜

時(shí)鐘

板上可編程時(shí)鐘振蕩器

SMA連接器，為收發(fā)器參考時(shí)鐘提供外部差分時(shí)鐘。

通用用戶輸入/輸出

DIP和按鍵式開關(guān)

LED

LCD

存儲(chǔ)器件

1-Gb同步閃存(主要用于存儲(chǔ)兩個(gè)FPGA配置——工廠和用戶配置)

板上存儲(chǔ)器

4個(gè)2-Gb DDR3 SDRAM

4個(gè)72-Mb QDR II SRAM

元件和接口

10/100/1000以太網(wǎng)PHY和RJ-45插頭

36個(gè)收發(fā)器通道

1個(gè)SFP+接口通道

1個(gè)具有EDC的SFP+接口通道

4個(gè)QSFP接口通道

10個(gè)CFP接口通道

20個(gè)Interlaken接口通道

溫度測(cè)量電路

管芯溫度

環(huán)境溫度

電源

14-V至20-V直流輸入

2.5-mm筒形插座，用于直流電源輸入。

On/off電源滑動(dòng)開關(guān)

板上電源測(cè)量電路

Quartus II軟件許可并沒有含在這一套件中

You can use this development kit to:

• Develop and test designs to interface with a variety of different optical modules.

• Develop and test Interlaken designs.

• Develop and test memory subsystems consisting of DDR3 or QDR II memory.

• Build designs capable of migrating to Altera’s HardCopy IV ASICs.


圖2.Stratix IV GT 100G開發(fā)板方框圖

圖3.Stratix IV GT 100G開發(fā)板外形圖

Stratix IV GT 100G開發(fā)板電路圖見:
Stratix IV GT 100G開發(fā)板電路圖.pdf

Stratix IV GT 100G開發(fā)板材料清單見:
Altera Stratix IV GT 100G開發(fā)板材料清單.xls

詳情請(qǐng)見:
http://www.altera.com.cn/literature/hb/stratix-iv/stx4_siv51001.pdf
和
http://www.altera.com.cn/literature/manual/rm_sivgt_100g_dev_board.pdf