中圖分類號：TN306 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.245650
中文引用格式： 王濤，于鵬，錢昀瑩. DSP片上Flash測試系統(tǒng)設(shè)計與實現(xiàn)[J]. 電子技術(shù)應(yīng)用，2025，51(2)：41-45.
英文引用格式： Wang Tao，Yu Peng，Qian Yunying. Design and implementation of DSP on-chip Flash testing system[J]. Application of Electronic Technique，2025，51(2)：41-45.

Design and implementation of DSP on-chip Flash testing system

Abstract： In the reliability screening and assessment test of DSP chip, the on-chip Flash erasure durability and data retention test is one of the most important tests. In view of the limitations of built-in self-test and external automated machine testing, this paper proposes the design and implementation of a test system for on-chip Flash of DSP chip. Based on the analysis of Flash fault types and test algorithms, the hardware schematic diagram and software implementation process are given, and a physical platform is built for effect evaluation. The test results show that the system can realize the on-chip Flash automatic test of multi position DSP chip without manual participation. At the same time, the working status can be displayed in real time, and the data and results in the test process can be automatically saved in the external memory, which is convenient for the statistical analysis of the test results in the later stage.

Key words : on-chip Flash；erasure durability；data retention；test system