中圖分類號：TN46 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234629
中文引用格式： 王亞軍，李俊龍，趙達(dá)，等. 基于RISC-V的硬件管理控制器設(shè)計(jì)[J]. 電子技術(shù)應(yīng)用，2024，50(6)：32-36.
英文引用格式： Wang Yajun，Li Junlong，Zhao Da，et al. Design of hardware management controller based on RISC-V[J]. Application of Electronic Technique，2024，50(6)：32-36.

Design of hardware management controller based on RISC-V

Abstract： With the development of advanced computing industries such as cloud computing and big data, implementing intelligent management based on hardware management mode is of great significance. A hardware management controller chip is designed and implemented on the RISC-V core, utilizing network communication tools to effectively manage application systems. A verification platform is built on UVM verification methodology for simulation verification, and a chip prototype verification platform is constructed on FPGA for collaborative verification and stability testing with the upper computer. The physical design adopts a 40 nm process with a design frequency of 250 MHz.

Key words : hardware management controller；intelligent management；RISC-V