中圖分類號：TN402 文獻標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.223442 中文引用格式： 崔明輝，王星，李娜，等. 一種基于CLASS-AB類運放的無片外電容LDO設(shè)計[J]. 電子技術(shù)應(yīng)用，2023，49(9)：53-57. 英文引用格式： Cui Minghui，Wang Xing，Li Na，et al. Design of a capacitor-less LDO based on CLASS-AB operational amplifier[J]. Application of Electronic Technique，2023，49(9)：53-57.
Design of a capacitor-less LDO based on CLASS-AB operational amplifier
Cui Minghui1，Wang Xing1，Li Na2，Xiang Lifeng1，Zhang Guoxian1
(1.No.58 Institue ， China Electronic Technology Group Corporation， Wuxi 214035， China； 2.School of IoT Engineering College， Jiangnan University， Wuxi 214122， China)
Abstract： This paper introduces a CLASS-AB OPAMP-based Low Drop Regulator (LDO) with no off-chip capacitor. Based on the high swing rate Error Amplifier (EA), a dynamic bias circuit has been constructed to feedback voltage to the internal dynamic bias transistors of EA, which greatly improves the LDO’s transient response capability. Moreover, the left half plane zero-pole introduced by the dynamic bias circuit ensures the LDO’s loop stability. At the same time, the EA adopts overshoot detection circuit to reduce the output overshoot and shorten the loop stability time. The circuit is designed and simulated based on 65 nm CMOS process. The simulation result shows that the LDO output is stable with no oscillation under the condition of 10 μA~50 mA load-current and 0~50 pF output capacitor. Under the condition of 2.5 V voltage input, 1.2 V voltage output, and no off-chip capacitor, if the load jumps between 10 μA and 50mA, the recovery time of LDO output is 0.7 μs and 0.8 μs, and the undershoot and overshoot voltages are 58 mV and 15 mV.
Key words : low dropout linear regulators；transient enhancement circuits；dynamic biasing circuits；no off-chip capacitors
