中圖分類號： TN402
文獻(xiàn)標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.222693
中文引用格式： 錢勁宇，強小燕，屈凌翔. 一種片上嵌入式Flash測試接口的設(shè)計[J].電子技術(shù)應(yīng)用，2022，48(10)：31-35.
英文引用格式： Qian Jinyu，Qiang Xiaoyan，Qu Linxiang. Design of an on-chip Flash memory test interface[J]. Application of Electronic Technique，2022，48(10)：31-35.

Design of an on-chip Flash memory test interface

Abstract： Flash has the charceteristics of low power consumption,large storage capacity and small volume,is widely used in embedded systems. Flash usually uses serial interface for erasing and programing test,which has the problems of low test efficiency and high test cost. The design and implementation of a test for Flash on chip is presented in this paper. By analyzing the interface and timing requirements of Flash on chip,a test interface based on multi-line SPI is designed,and the parallel test designed of Flash memories is realized under the condition of ensuring stability,which improves the test speed. The NCverilog simulation results show that the design effectively shortens the test time,meets the test requirements,and is successfully applied to a 32-bit floating-point microprocessor.

Key words : Flash；test interface；test speed；microprocessor