中圖分類號： TN401
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.212329
中文引用格式： 鄧佳偉，張梅娟，王琪，等. PowperPC架構(gòu)下USB3.0的IP核軟硬件協(xié)作驗證[J].電子技術應用，2022，48(5)：37-41.
英文引用格式： Deng Jiawei，Zhang Meijuan，Wang Qi，et al. Hardware/software co-verification of USB3.0 IP core under PowerPC architecture[J]. Application of Electronic Technique，2022，48(5)：37-41.

Hardware/software co-verification of USB3.0 IP core under PowerPC architecture

Abstract： With the increasing requirement of transmission rate of USB,the traditional PowerPC processor based on the USB2.0 can not meeet the requirements of high speed and large-capacity transmission.The paper presents a solution of USB 3.0 base on PowerPC processor architecture. By comparing USB3.0 and USB2.0, USB3.0 has higher transmission rate.By cooperating with the high preformance PowerPC processor, the transfer capability of the USB controller is improved significantly, and ther PowerPC computing resources are fully utilized.This paper describes a programme of USB3.0 IP core based on the PowerPC architecture. Finally the the method of hardware/softeware cooperative verification is used to verfiy the feasibility of the design,which lays a technical foundation of subsequent chip design and verification.

Key words : PowerPC；universal serial bus 3.0；Linux；hardware/software co-design technology；IP Core