中圖分類號： TN911.72；TN4 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.211411 中文引用格式： 郭鳴晗，陳立平，張浩，等. 自適應(yīng)定階的快速Burg算法設(shè)計與FPGA實現(xiàn)[J].電子技術(shù)應(yīng)用，2021，47(11)：62-67，72. 英文引用格式： Guo Minghan，Chen Liping，Zhang Hao，et al. Design and FPGA implementation of fast Burg algorithm of adaptive order determination[J]. Application of Electronic Technique，2021，47(11)：62-67，72.
Design and FPGA implementation of fast Burg algorithm of adaptive order determination
1.University of Chinese Academy of Sciences，Beijing 100049，China； 2.Institute of Microelectronics of Chinese Academy of Sciences，Beijing 100029，China
Abstract： Aiming to real-time requirement of signal spectrum analysis, an adaptive ordering of fast Burg algorithm hardware acceleration circuit for short sequence based on FPGA is designed. The fast Burg algorithm combined with FPE criterion can be used to determine the order of AR parameters. The parallel two-stage pipeline structure with flexible control is realized, and the parallel computing unit is parallelized. At the same time, the storage unit is optimized to achieve the balance between speed and area. The test show that the algorithm can accurately estimate the signal frequency for short sequences. Compared with the calculation time of Burg algorithm hardware implementation scheme, this algorithm reduces the calculation time by 75%, which does play a role of acceleration, and saves memory space. So, this design meets the design requirements.
Key words : AR parameter model；Burg algorithm；fast Burg algorithm；FPGA；hardware acceleration
