EDA業(yè)內(nèi)矚目的年度活動Cadence用戶大會CDNLive將于2012年8月9日于北京香格里拉酒店召開，主辦方擬邀請400家客戶參加大會，本土最大分銷商科通集團作為Cadence中國區(qū)最大增值代理商，將以贊助商名義參加大會，演示代理的Cadence PCB全線(Allegro和OrCAD)產(chǎn)品，幫助本土工程師利用高級EDA軟件加速產(chǎn)品設計。
科通集團自2011年1月1日起正式與Cadence公司開展分銷合作，科通集團在中國區(qū)授權分銷Cadence的OrCAD 及Allegro全線產(chǎn)品?？仆ìF(xiàn)已擁有包括Microsoft、Intel、Panasonic、Freescale 、Xilinx、SanDisk、Linear及Broadcom等在內(nèi)的多條產(chǎn)品線，在無線通信、電信設備、企業(yè)網(wǎng)絡、數(shù)字媒體、家庭娛樂、汽車電子、工業(yè)控制等領域擁有很高的市場份額。深圳、香港、北京、上海、南京、武漢、西安、成都、廈門等多個分公司及辦事處構成了覆蓋全國的銷售和服務網(wǎng)絡，有超過500名高素質(zhì)員工為國內(nèi)的OEM廠商、ODM廠商和EMS廠商提供范圍廣泛的電子元器件銷售及方案提供服務。
Cadence用戶大會至今已經(jīng)舉辦7屆，每年的Cadence用戶大會關注EDA領域的年度熱點，以論文演講、技術演示、趨勢演講、產(chǎn)品演示的方式全面展示EDA領域的最新技術和方案，大會也提供了交流的平臺，方便與會者交流設計心得、解決設計難題。
2012年度Cadence用戶大會將于2012年8月9日在北京香格里拉酒店舉行。本次年會聚集了Cadence技術用戶、開發(fā)商和業(yè)內(nèi)專家。與會者將從業(yè)內(nèi)同仁處了解應對未來電子設計挑戰(zhàn)的新思路和解決方案。也可以通過論文演講與其他地區(qū)的半導體設計者分享重要設計與驗證問題的解決經(jīng)驗，并為實現(xiàn)高級晶片、SoC和系統(tǒng)發(fā)現(xiàn)新技術。
本次年度大會為免費活動，歡迎業(yè)內(nèi)人士踴躍報名，在線注冊地址：
http://www.cadence.com/cn/cadence/events/Pages/registration.aspx?eventid=106
如有任何疑問，請發(fā)送郵件至event_cn@cadence.com
會議日程安排：（2012年8月9日, 星期四）
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08:30-09:00 |
Registration and morning light breakfast |
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09:00-09:05 |
Opening Ceremony |
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James Liu, GM & VP sales, Cadence Design Systems |
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09:05-09:25 |
Keynote: Opportunities, Challenges, and Collaboration |
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Lip-Bu Tan, President and CEO, Cadence Design Systems |
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09:25-09:50 |
Keynote presentation |
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Dr. Wei Shaojun, Director, Institute of Microelectronics, Tsinghua University |
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09:50-10:15 |
Keynote: Realizing Best Performance, Power, Area, and Yield for the 2x Nanometer Era |
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Chi-Ping Hsu, Senior VP R&D, Cadence Design Systems |
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10:15-10:30 |
Morning Break |
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(Demo booth & Exhibition open) |
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10:30-11:55 |
Panel discussion (Theme: Aggregate or Disaggregate? Chinese semiconductor industry trend in the next 10 years) |
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Moderator: Charlie Huang, Senior VP, Worldwide Field Operations, Cadence Design Systems; 6 key executive panelists from China IC Ecosystem |
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11:55-12:00 |
Best Paper Award Ceremony |
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12:00-13:00 |
Lunch |
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(Demo booth open during 12:30-13:00) |
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Digital |
Custom/Analog |
System Design & Functional Verification |
IC Packaging and PCB Design |
Design & Verification IP |
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13:00-13:30 |
D-01 Encounter RTL-to-Signoff technology overview and roadmap --Cadence |
C-01 Custom Design And Simulation (CAS) Technology Overview --Cadence |
S-01 Functional Verification Overview --Cadence |
P-01 PCB and IC Packaging Technology Overview including Introduction of Sigrity Technology --Cadence |
I-01 Design & Verification IP technology overview --Cadence |
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13:30-14:00 |
D-02 Cadence Silicon Signoff and Verification Solutions Update--Cadence |
C-02 PVS: design and signoff with confidence--Cadence |
S-02 Next generation SoC co-development with Cadence’s System Development Suite--Cadence |
I-02 Reducing IC size, power and cost through early chip planning --Cadence |
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14:00-14:25 |
D-03 Customer Presentation --ARM |
C-03 Block and Chip level AMS Designer verification --NationalZ |
S-03 A comprehensive approach to scalable Framework for both vertical and horizontal reuse in UVM verification --AMD |
P-02 A new Methodology of Power Design and Analysis with Allegro PCB PDN --Ericsson |
I-03 customer presentation --ZTE |
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14:25-14:50 |
D-04 The implementation of Smartphone chip including Cortex TM-A5 core at Cadence Platform --Spreadtrum |
C-04 Using RelXpert to do performance degradation and lifetime simulation on mos device --Analogix |
S-04 Best Practice of Wreal Based Analog Modeling --LSI |
P-03 Building a PCB design quality assurance system —Huawei |
I-04 Customer presentation --Brite Semi |
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科通集團是中國本土最大、成長最快、關注增值服務的電子元器件及方案提供商，與全球主要的領先半導體供應商緊密合作，例如Broadcom、Xilinx、Freescale、Linear、Atmel、Intel、Microsoft、Sandisk等等，致力于為國內(nèi)的OEM廠商、ODM廠商和EMS廠商提供范圍廣泛的電子元器件和技術支持服務,應用涉及智能手機、消費電子、工控醫(yī)療、汽車及智能交通系統(tǒng)、網(wǎng)絡通信等眾多領域。歡迎聯(lián)絡科通集團各地辦事處，總部電話：0755-26743210，如需了解更多信息，請訪問科通集團網(wǎng)站：www.comtech.com.cn，或關注科通官方微博：@comtech科通.