中圖分類號：TN911.8 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.234094
中文引用格式： 常健，郭永剛，蔡志偉，等. 一種用于頻率駕馭系統(tǒng)的快速捕獲鎖相環(huán)設(shè)計[J]. 電子技術(shù)應(yīng)用，2024，50(2)：111-116.
英文引用格式： Chang Jian，Guo Yonggang，Cai Zhiwei，et al. Design of a fast-acquisition phase-locked loop for frequency control systems[J]. Application of Electronic Technique，2024，50(2)：111-116.

Design of a fast-acquisition phase-locked loop for frequency control systems

Abstract： Phase-locked loop (PLL) is a negative feedback control system that can achieve phase synchronization of two signals. Its filtering effect can make its passband narrow, and its output frequency automatically track the input frequency. Phase locked loops are often used in atomic clocks, frequency standard taming systems, and time synchronization systems. PLL is an important component of communication, satellite navigation, and electrical measurement systems. Phase noise and acquisition time are two mutually constraining indicators in a PLL. Reducing the frequency acquisition time of a PLL while suppressing phase noise is one of the important issues in current research on phase-lock techniques. To solve this problem, this paper designs an auxiliary acquisition circuit based on the basic theory and composition of analog PLL and the mathematical relationship between loop bandwidth and acquisition time.

Key words : PLL；phase noise；acquisition