中圖分類號：TP391 文獻(xiàn)標(biāo)志碼：A DOI: 10.16157/j.issn.0258-7998.233886
中文引用格式： 陶青平，沈婧. 基于UVM和C語言驗(yàn)證JTAG調(diào)試協(xié)議的研究與實(shí)現(xiàn)[J]. 電子技術(shù)應(yīng)用，2023，49(10)：112-117.
英文引用格式： Tao Qingping，Sheng Jing. Design and implementation for JTAG protocol test based on UVM and C[J]. Application of Electronic Technique，2023，49(10)：112-117.

Design and implementation for JTAG protocol test based on UVM and C

Abstract： In IC verification,due to the complexity and multiplicity of the JTAG protocol,the code written separately in TestBench for verification is long and difficult to maintain.Sometimes some companies and groups put this part of verification in FPGA prototype verification.In prototype verification,some modules need to be replaced,which cannot be guaranteed to be the same as the RTL level netlist.It may lead to the failure of chip tog debugging after streaming.In view of this situation,this paper proposes an implementation method for joint verification of JTAG debugging protocol based on UVM and C language.Combining the universality of UVM methodology and the convenience of C language,UCM builds a framework for verification of JTAG protocol,C language verification of chip JTAG protocol is realized by calling the chip JTAG interface implemented on the UVM side to drive the timing.

Key words : UVM；FPGA prtotype verification；C language；JTAG protocol