中圖分類號(hào)： TN702
文獻(xiàn)標(biāo)識(shí)碼： A
DOI：10.16157/j.issn.0258-7998.211472
中文引用格式： 錢勇，劉威. HDLC數(shù)據(jù)幀并行搜幀解封裝模塊的設(shè)計(jì)與驗(yàn)證[J].電子技術(shù)應(yīng)用，2022，48(1)：80-83.
英文引用格式： Qian Yong，Liu Wei. Design and verification of HDLC data frame parallel search and decapsulation module[J]. Application of Electronic Technique，2022，48(1)：80-83.

Design and verification of HDLC data frame parallel search and decapsulation module

Abstract： The HDLC signal link is the high level data link control(HDLC) developed by the international organization for standar- dization(ISO). The article follows the HDLC standard data link layer specification, uses the hardware description language Verilog HDL to implement a parallel structure-based HDLC frame search and decapsulation circuit, and uses System Verilog technology to build a verification platform, and randomly generates HDLC data frames to verify the correctness of the design. Using Modelsim software to simulate waveforms, during the simulation process, for HDLC data frames with a payload area of 10 bytes, the decoder circuit requires 16 clock cycles to complete the work, taking into account processing speed and flexibility. Using QuartusII software synthesis, on Altera CycloneV devices, the circuit uses 8 adaptive logic modules ALM, 24 registers, and 35 pins.

Key words : HDLC protocol；frame search and decapsulation；System Verilog；Modelsim