摘要： HDLC信號鏈路是國際標準化組織(ISO)制定的高級數(shù)據(jù)鏈路的控制規(guī)程(High Level Data Link Control，HDLC)。遵循HDLC標準數(shù)據(jù)鏈路層規(guī)范，采用硬件描述語言Verilog HDL實現(xiàn)了一種基于并行結(jié)構(gòu)的HDLC搜幀解封裝電路，并采用System Verilog技術(shù)搭建驗證平臺，隨機生成HDLC數(shù)據(jù)幀來驗證設(shè)計正確性。使用Modelsim軟件仿真波形，在仿真過程中，對于凈荷區(qū)數(shù)據(jù)長度為10個字節(jié)的HDLC數(shù)據(jù)幀，解碼器電路工作完成需要16個時鐘周期，兼顧了處理速度和靈活性。使用QuartusII軟件綜合，在Altera CycloneV器件上，電路使用了8塊自適應(yīng)邏輯模塊ALM，24個寄存器，35個引腳。
中圖分類號： TN702 文獻標識碼： A DOI：10.16157/j.issn.0258-7998.211472 中文引用格式： 錢勇，劉威. HDLC數(shù)據(jù)幀并行搜幀解封裝模塊的設(shè)計與驗證[J].電子技術(shù)應(yīng)用，2022，48(1)：80-83. 英文引用格式： Qian Yong，Liu Wei. Design and verification of HDLC data frame parallel search and decapsulation module[J]. Application of Electronic Technique，2022，48(1)：80-83.
Design and verification of HDLC data frame parallel search and decapsulation module
Qian Yong，Liu Wei
School of Physics Science and Technology，Wuhan University，Wuhan 430072，China
Abstract： The HDLC signal link is the high level data link control(HDLC) developed by the international organization for standar-
dization(ISO). The article follows the HDLC standard data link layer specification, uses the hardware description language Verilog HDL to implement a parallel structure-based HDLC frame search and decapsulation circuit, and uses System Verilog technology to build a verification platform, and randomly generates HDLC data frames to verify the correctness of the design. Using Modelsim software to simulate waveforms, during the simulation process, for HDLC data frames with a payload area of 10 bytes, the decoder circuit requires 16 clock cycles to complete the work, taking into account processing speed and flexibility. Using QuartusII software synthesis, on Altera CycloneV devices, the circuit uses 8 adaptive logic modules ALM, 24 registers, and 35 pins.
Key words : HDLC protocol；frame search and decapsulation；System Verilog；Modelsim
