中圖分類號： TN722.3
文獻標識碼： A
DOI：10.16157/j.issn.0258-7998.211497
中文引用格式： 饒忠君，張志浩，章國豪. 2.3～2.7 GHz雙模式低噪聲射頻接收前端全集成芯片的設(shè)計[J].電子技術(shù)應用，2021，47(7)：17-20，47.
英文引用格式： Rao Zhongjun，Zhang Zhihao，Zhang Guohao. Design of a 2.3～2.7 GHz dual-mode low-noise RF receiver front end[J]. Application of Electronic Technique，2021，47(7)：17-20，47.

Design of a 2.3～2.7 GHz dual-mode low-noise RF receiver front end

Abstract： A fully-integrated dual-mode low-noise RF receiver front-end for the 2.3 GHz～2.7 GHz band was presented based on a GaAs pHEMT technology. The receiver front-end consists of a single-pole double-throw(SPDT) transmit-receive switch and a low-noise amplifier(LNA)with bypass mode. The cascode common-source structure with inductive degeneration topology is adopted to achieve the LNA.The SPDT switch is embedded into the input matching network as a concurrent design to realize high Q matching network with minimum components for low noise, high gain and superior input return loss matching. Concurrent design of multiple switches for Bypass function is utilized to attenuate the high input power transmissions. The measurement results show that the presented FEM exhibits low noise figure of 1.53～1.64 dB and gain of 18.1～19.2 dB for 2.3～2.7 GHz frequency range in the high-gain LNA mode. At 2.5 GHz, the tested input 1 dB compression point at 2.5 GHz is -1.5 dBm. The insertion loss in Bypass mode typically varies from 6 to 7 dB in the operation frequency bands.

Key words : GaAs pHEMT；low noise amplifier；low noise；dual mode