受到物理限制，電子工程師必須構(gòu)想出更加精巧的晶體管 
1965年，戈登•摩爾預(yù)言，在一定大小的芯片上所能容納的晶體管的數(shù)量每兩年就會增加一倍，這就是所謂的摩爾定律。多年來這個定律一直在發(fā)揮作用。第一個集成電路（由德州儀器的杰克•基爾比發(fā)明，見圖）還只是一個笨拙不堪的大家伙，而現(xiàn)在晶體管已需用納米（1米的十億分之一）來計量。人們以摩爾定律的發(fā)展速度創(chuàng)造了快速而智能化的計算機，圖案漂亮并將世界聯(lián)接在了一起。從摩爾博士創(chuàng)立這個定律的時候起，人類就進入了一個不可思議的信息技術(shù)時代。本來一個不經(jīng)意的發(fā)現(xiàn)竟有如此強大的生命力。
其實它并不是一條真正的定律，而只是一種現(xiàn)象，一種對技術(shù)發(fā)展漫漫征程的描述，發(fā)展的每一步都包含著具體的技術(shù)變革（見圖表）。技術(shù)發(fā)展勢不可擋，已成預(yù)言般的信條。晶體管的每一次“縮身”，都是朝著它們的最小尺寸邁進了一步。如果按此定律繼續(xù)發(fā)展， 20年之內(nèi)，晶體管將會與幾個單晶硅原子大小相當。
說得更精確一點，晶體管已經(jīng)很小很小，在這樣大小的空間中每個原子都變得舉足輕重。原子太少它們之間的絕緣性消失，或者因 “量子隧穿”現(xiàn)象（一種電子自然消失、并在他處重現(xiàn)的現(xiàn)象）將電流泄漏到本不該流向的地方。不適當種類的原子太多效果同樣不妙，這會影響晶體管的導(dǎo)電性。因此工程人員正在努力重新設(shè)計晶體管。這樣看來，摩爾的預(yù)言在未來的一段時間里還將繼續(xù)有效。
原子核母板
晶體管實際上是一個電子控制的轉(zhuǎn)換器，它由4部分組成：源極（電流從該極流入），漏極（電流從這里流出），（連接源極和漏極的）溝道以及柵極（通過電壓的變化控制通道的開關(guān)）。在傳統(tǒng)的晶體管中，這些組件都分布在同一個平面上。要防止漏電，一種思路就是把晶體管改為三維設(shè)計。
制造一個從母體芯片上伸出來的晶體管可以使許多組成原子的布置更加有效，特別是那些構(gòu)成了通道和柵極的原子。將通道外伸、三面圍以柵極原子，這樣就能夠增加?xùn)艠O的表面積，更好地控制通道，并減少泄漏。在導(dǎo)通狀態(tài)下，晶體管柵極的功能越是優(yōu)良，通過的電流就越大。
五月份，美國著名的芯片巨頭英特爾（摩爾博士也是該公司創(chuàng)建人之一）宣布一項計劃，對這種營銷時冠以“三柵極”的技術(shù)設(shè)備進行商業(yè)性開發(fā)。公司預(yù)計，新晶體管將于今年晚些時候面世，這種晶體管比現(xiàn)有的晶體管省電一半，特別適合于筆記本電腦使用，畢竟，電池壽命是筆記本電腦的一大賣點。
全面改用三維模式，這在一個成熟的行業(yè)內(nèi)很難推廣，畢竟他們的二維模式已經(jīng)成熟。包括美國公司Globalfoundries、英國公司ARM在內(nèi)的絕緣硅聯(lián)合會，試圖把提高平板晶體管作為他們的一個替代方案，該聯(lián)合會的技術(shù)是把在一個純硅片薄層內(nèi)部制作晶體管，這層純硅下面是一個絕緣層，再下面是一個標準晶片，這個標準晶片被用作基底，用來安放晶體管。這種方法要把晶體管的溝道做得足夠薄，使柵極產(chǎn)生的電磁場能夠透過整個溝道，提高柵極所能發(fā)揮的最大控制力。但這種方法迫使絕緣硅聯(lián)合會必須面對晶體管尺寸不斷縮小而產(chǎn)生的第二個問題：偏離正常位置的原子要么太多，要么太少。
為了改善電子性能，制造晶體管所用的硅材料中常需摻入其他元素 。最新的晶體管尺寸非常小，在其溝道中摻雜只要往硅中注入少量雜質(zhì)原子，如果這個量掌握得不好，晶體管的正常運行就會受到影響。但制造過程中的偏差使得這種要求很難達到。絕緣硅聯(lián)合會希望使用的超薄溝道摻入雜質(zhì)的工藝極其困難，因此，他們決定不向硅中摻入雜質(zhì)，而用純凈硅來制造晶體管的溝道。但這要求硅層厚度不能超過5納米。而且在整個晶片上這個厚度幾乎要保持一致，英特爾公司（應(yīng)當承認，它并不是一個心平氣和的旁觀者）認為，如此精準的標準，肯定會增加晶體管的制造成本。
SuVolta是硅谷的一家小公司，他們提出了另一種方法。他們計劃制造的平板晶體管通道也不摻入雜質(zhì)。但這家公司打算使用價格低廉的傳統(tǒng)硅晶片，而不必改變晶片的成分，不必制造絕緣硅聯(lián)合會要求的超薄溝道，他們的過人之處在于，在溝道的下面增加一個柵極。兩個柵極共同作用就能夠控制沒有添加雜質(zhì)并且厚度不夠小的溝道。就這樣，功能更好而能耗更低的晶體管就產(chǎn)生了，該公司表示，它的能耗減少到只有傳統(tǒng)類型的晶體管能耗的一半，而性能上并沒有損失。SuVolta此舉激起了日本電子巨頭富士通的極大興趣，目前他們已擁有這項技術(shù)的生產(chǎn)許可。
還有多少發(fā)展空間
所有這些方法都意味著摩爾定律至少在未來幾年內(nèi)還會繼續(xù)發(fā)揮作用。數(shù)百位專家每年都要對半導(dǎo)體國際技術(shù)路線圖進行更新。他們預(yù)測，標準晶體管的橫向尺寸到2013年將減小到16納米（現(xiàn)在是32納米），到2015年還將減小到11納米。要想進一步縮小就需要一個概念上的飛躍。有幸的是，已經(jīng)有了幾個這樣的選擇。
一個最有前景的方法去年已由考林吉帶領(lǐng)的愛爾蘭廷德爾國家研究所描繪出來。他們發(fā)表一篇論文，宣布他們已經(jīng)創(chuàng)造出無接晶體管。這一方法早在1925年就由一位名叫朱利葉斯•利林菲爾德的物理學(xué)家獲得專利，但直到現(xiàn)在，它的制造依然是個難題。
晶體管連接處的兩面是摻入了導(dǎo)電電子（因為電子帶有負（negative）電荷，因此被稱為n型材料）的硅片，而p型區(qū)域的晶格中摻入了帶有正電的空穴，這些空穴由電子的游離而產(chǎn)生。還有一些三極管，源極和漏極都是p型，溝道是n型。在其他情況下，情況正好相反。在n型和p型的結(jié)合處，硅的作用就像一個閥門，防止電流流向相反的方向。
然而，晶體管越小，制造PN結(jié)的難度就越大，這也是受到了摻入元素濃度波動的影響。考林吉博士的設(shè)計——類似英特爾的三柵極，在一個單獨的、超薄的硅導(dǎo)線周圍環(huán)繞一個三維柵極——為避免這種情況，整個晶體管全部采用一種比常規(guī)平板晶體管所用的半導(dǎo)體摻入元素濃度更大的半導(dǎo)體來制造。設(shè)計中含有一個極薄的溝道，就像閥門一樣，斷路時載流子（比如，自由電子或空穴）全部消失，通路時充滿這種載流子。它的尺寸同樣應(yīng)該可以縮小。廷德爾研究院的研究人員去年報告說，通過對這種原子排列的無接晶體管進行計算機模擬顯示他們的運行狀況完好，而且它的柵極長度只有3.1納米。
這種柵極長度會使摩爾定律在未來幾年將繼續(xù)發(fā)揮作用，此后，摩爾定律要想繼續(xù)發(fā)揮作用，就要求有更多的創(chuàng)新思維。比如，大量的學(xué)術(shù)人員和工程人員正在思考，如何制造出這樣一種晶體管，使得量子溝道成為一種特色，而不是一種缺陷。根據(jù)量子理論，電子只有在某個能量級才能獲得，這就意味著利用隧穿效應(yīng)的晶體管可能直接從從弱電流轉(zhuǎn)至強電流，并且不要預(yù)熱時間。
這也許是一個不錯的想法。晶體管的大小受到單原子大小的局限，在這種情況下，還不知這是否就是工程人員最后一個即興之舉。當摩爾博士宣布這一定律時，他本以為定律可能會在10年內(nèi)有效。具有不可抗拒力量的人類創(chuàng)造力確保摩爾定律的壽命比預(yù)想的大大延長了，但這種力量現(xiàn)在正面臨著原子物理學(xué)難以逾越的障礙。這真是一場引人入勝的競賽。(編譯：Kevin)
附原文：Plugging the leaks
As physical limits bite， electronic engineers must build ever cleverer transistors
Aug 20th 2011 | from the print edition
MOORE’S LAW—the prediction made in 1965 by Gordon Moore， that the number of transistors on a chip of given size would double every two years—has had a good innings. The first integrated circuit （invented by Jack Kilby of Texas Instruments， see above） was a clunky affair. Now the size of transistors is measured in billionths of a metre. Moore’s law has yielded fast， smart computers， with pretty graphics and worldwide connections. It has thereby ushered in an age of information technology unimaginable when Dr Moore coined it. Not bad going for what was originally just an off-the-cuff observation.
That observation， however， is not truly a law. It is， rather， the description of a journey of many steps， each a specific technological change （see chart below）。 That new steps will happen is as much an article of faith as a prediction. Every time transistors shrink， they get closer to the point where they can shrink no further—for if the law continues on its merry way， transistors will be the size of individual silicon atoms within two decades.
More to the point， they have already shrunk to a size where every atom counts. Too few atoms can cause their insulation to break down， or allow current to leak to places it is not supposed to be because of a phenomenon called quantum tunnelling， in which electrons vanish spontaneously and reappear elsewhere. Too many atoms of the wrong sort， though， can be equally bad， interfering with a transistor’s conductivity. Engineers are therefore endeavouring to redesign transistors yet again， so that Dr Moore’s prediction can remain true a little longer.
Atom heart motherboard
A transistor is an electrically operated switch composed of four pieces： a source （where current enters）， a drain （where it leaves）， a channel （which links the two） and a gate （which opens and shuts the channel by varying in voltage）。 In a conventional transistor， these components lie in about the same plane. One idea for dealing with leaks is to change that by moving transistor design into three dimensions.
Building a transistor that sticks out of its parental chip lets many of its component atoms be deployed more usefully—particularly those that constitute the channel and the gate. By sticking the channel into the air and surrounding it on three sides with the atoms of the gate， you increase the surface area of the gate. That gives better control of the channel and reduces leaks. Having a better-functioning gate also lets more current flow when the transistor is on.
In May Intel， an American chip giant （co-founded， as it happens， by Dr Moore）， announced plans to commercialise a technological fix of this sort under the marketing name “Tri-Gate”。 The company reckons the new transistors， which should be available later this year， will consume half as much power as its existing offerings， making them particularly suitable for mobile computing， where battery life is an important selling point.
A universal change to three dimensions， though， will be difficult to sell to an industry that has grown up thinking in two. As an alternative the Silicon On Insulator （SOI） consortium， which includes Globalfoundries， an American firm， and ARM， a British one， is trying to improve flat transistors. The consortium’s technology builds its transistors inside a sliver of pure silicon， laid on top of an insulator， which in turn sits on top of a standard wafer， the substrate on which transistors are constructed. The idea is to make the channel as thin as possible， allowing the electric field generated by the gate to penetrate the entire thing， thus improving the control that the gate is able to exert. But this approach also forces the consortium to tackle the second problem raised by the continual shrinkage of transistors： too many or too few atoms in the wrong places.
The silicon of which transistors are made is frequently doped with other elements， to affect its electrical properties. The latest devices， though， are so small that doping their channels involves placing just a handful of dopant atoms among the silicon. Get the number wrong， and things will not work properly. But fluctuations in the manufacturing process make the required consistency hard to achieve. Correctly doping the ultra-thin channels that the consortium hopes to use is simply too difficult—hence the decision to do without dopants altogether and build channels out of pure silicon. But the design requires that this silicon layer be no more than five nanometres （billionths of a metre） deep. That figure， moreover， must be almost constant across the entire wafer—an exacting standard which Intel （admittedly， not a dispassionate observer） believes will add to manufacturing costs.
SuVolta， a small company in Silicon Valley， has therefore come up with a third approach. It， too， plans to build flat transistors with undoped channels. But it will do so on conventional， cheap silicon wafers without the need for the modified wafers or ultra-thin channels required by the SOI consortium， a trick it accomplishes by adding a second gate beneath the channel. In concert， the two gates are able to control the undoped channel without its having to be ridiculously thin. Once again， the result is better-behaved transistors and reduced power consumption—as little as half that demanded by old-style transistors， says the firm， with no loss of performance. SuVolta has already piqued the interest of Fujitsu， a Japanese electronics giant， which has licensed the technology.
Room at the bottom
All these approaches mean that Moore’s law should be able to chunter along for a few more years， at least. The International Technology Roadmap for Semiconductors， which is updated every year by a team of several hundred experts， predicts that standard transistors will be 16 nanometres across by 2013 （at the moment， 32 nanometres is the standard） and 11 nanometres by 2015. To go smaller than this， though， will require yet another conceptual leap. Fortunately， there are several on offer.
One promising approach was outlined last year by a team at the Tyndall National Institute in Ireland， led by Jean-Pierre Colinge. They published a paper announcing the creation of a junctionless transistor—an idea patented in 1925 by a physicist called Julius Lilienfeld， but which was， until recently， too difficult to manufacture.
The junctions in a transistor are between bits of silicon doped to conduct electrons （known as n-type material， because electrons are negatively charged）， and p-type areas doped to conduct positively charged holes in the crystal lattice， which are places where electrons should be， but aren’t. In some transistors， source and drain are p-type， and channel n-type. In others the reverse is true. The junctions between n- and p-type silicon act like valves， stopping current flowing in the wrong direction.
As transistors get smaller， however， laying down n-type and p-type materials in proximity gets harder， thanks once again to fluctuations in the concentrations of dopants. Dr Colinge’s design—which， like Intel’s Tri-Gate， clamps a 3D gate around a single， ultra-thin silicon wire—avoids this by building the entire device from a single type of semiconductor， with much higher dopant concentrations than a conventional flat transistor. The design incorporates a channel thin enough to become entirely devoid of carriers （ie， free electrons or holes） when switched off， thus acting as a valve， yet full of them when switched on. It should be shrinkable， too. The Tyndall Institute’s researchers reported last year that atom-by-atom computer simulations of junctionless transistors with a gate length of just 3.1 nanometres show that they ought to work perfectly.
Such a gate length would keep Moore’s law rolling for several years. To carry on beyond that， however， requires even more exotic thinking. A number of groups of academics and engineers， for example， are pondering how to make transistors in which quantum tunnelling is a feature rather than a bug. Quantum theory dictates that electrons are available only at certain energy levels， which means that a transistor which harnessed the tunnelling effect could switch directly from a low current （off） to a high current （on）， with no ramp-up time.
That would be a neat trick. Whether it would be the last one up the engineers’ sleeves， as the single-atom limit looms， remains to be seen. When he first promulgated it， Dr Moore thought his law might endure for ten years. The irresistible force of human ingenuity has ensured it has done far better than that. But that force is now up against the immovable object of atomic physics. It is a fascinating contest.