內部可編程低通濾波器提供經典的RC振蕩器設計方案。

　　可編程邏輯設備在數字設計中提供實現(xiàn)復雜功能的通用方法。雖然廠商還沒有提供與VLSI數字電路相比更復雜的模擬電路，但現(xiàn)場可編程模擬電路被廣泛用于信號調理和濾波器的應用?；贑MOS運算跨導放大器和開關電容放大器，這些設備提供了解決相對復雜設計的簡單方案。Lattice半導體公司（www.latticesemi.com) 的在系統(tǒng)可編程模擬器件ispPAC20和配套的PAC設計軟件提供電路設計和確認的簡便方法（參考文獻1）。本設計方案提出基于ispPAC20的兩個簡單正弦振蕩器設計方法。

　　ispPAC10內部電阻固定在250 kΩ標稱值上，所有電容由用戶在1.07到61.59 pF之間選擇。圖1表示ispPAC10內部1、2和4模塊被連接成級聯(lián)的三個一階低通濾波器，形成經典相位偏移RC振蕩器。改變電容值產生超過18到130kHz范圍的振蕩頻率。每個PAC模塊增益被設置成2，從而獲得-8的回路增益，這是振蕩器的Barkhausen條件需要的（參考文獻2）。配置模塊3，一階低通濾波器減少了振蕩器輸出的THD（總諧波失真）。模塊3的電容值使濾波性能達到最優(yōu)化，由此造成相位偏移不同。

　　圖2中電路描述了雙積分器回路形成經典的求積RC振蕩器。電路振蕩器頻率跨越從12到126 kHz，依靠模塊1、2形成積分器的時間常數。理論上，每個積分器增益本該有個統(tǒng)一的絕對值，但實際上，ispPAC給出詳細說明除了反向積分器，模塊1中產生穩(wěn)定的正弦信號所需要的至少-4增益。電路使用-10的增益。ispPAC10設備的兩個附加模塊形成能夠降低輸出THD的二階低通濾波器。在兩個振蕩器電路中，改變低通濾波器增益，以便在所有頻率的電路輸出都可以傳遞特殊的電壓，例如1V峰峰值。

　　表1和表2分別包含相位偏移、求積振蕩器器件和輸出特性的概要。電容值CN以頻率f0在振蕩器n次PAC模塊中使用。設計使用Tektronix TDS1002數字振蕩器的FFT功能，測量THD和中心頻率f0，即-20 dB水平下每個輸出頻率的頻譜線寬度。

　　圖3說明了基于ispPAC振蕩器的微處理器對不同頻率的動態(tài)重置的應用。非易失性存儲器存儲每個ispPAC10電路模塊特殊頻率的電容和增益值。數據傳輸通過ispPAC10的串行測試存取口接口，使用IEEE 1149.1 JTAG標準協(xié)議進行傳輸。

　　英文原文：

　　Programmable analog circuits yield single-chip sinusoidal oscillators

　　Internally programmed low-pass filters yield classic RC oscillator.

　　Stefano Salvatori and Paolo Lorenzi, University of Rome, Rome, Italy; Edited by Brad Thompson and Fran Granville -- EDN, 1/19/2006

　　Programmable-logic devices provide a popular method of implementing complex functions in digital designs.

Although manufacturers don't yet offer analog circuits whose complexity compares to VLSI digital circuits, field-programmable analog circuits are enjoying extensive use in signal-conditioning and filtering applications. Based on CMOS-operational-transconductance and switched-capacitor amplifiers, these devices offer a convenient approach to relatively complex design problems. Lattice Semiconductor's (www.latticesemi.com) ispPAC10 in-system-programmable analog circuit and its accompanying PAC Designer software offer a convenient method of circuit design and verification (Reference 1). This Design Idea presents two simple sinusoidal oscillators based on the ispPAC10.

　　Resistors within the ispPAC10 are fixed at a nominal 250 kΩ, and all capacitors are user-selectable from 1.07 to 61.59 pF. Figure 1 shows an ispPAC10 with its internal blocks 1, 2, and 4 connected as a cascade of three first-order lowpass filters to form a classic phase-shift RC oscillator. Altering the capacitors' values produces oscillation frequencies over a range of 1

8 to 130 kHz. Each PAC block's gain is fixed at a factor of two to obtain a loop gain of –8, which Barkhausen's condition for oscillation requires (Reference 2). Configured from Block 3, a first-order lowpass filter reduces the THD (total harmonic distortion) on the oscillator's output. The values of capacitors in Block 3 are optimized for filtering performance and thus differ from those of the phase-shift stages.

　　The circuit in Figure 2 describes a two-integrator loop that forms a classic quadrature-RC oscillator. The circuit's oscillation frequency spans 12 to 126 kHz and depends on the time constants of the integrators that blocks 1 and 2 form. In theory, each integrator's gain should have an absolute value of unity, but, in practice, ispPAC allows specification only of inverting integrators, and producing a stable sinusoidal signal requires a gain of at least –4 in Block 1. The circuit uses a gain of –10. Two additional blocks of the ispPAC10 device form a second-order lowpass filter that decreases the output's THD. In both oscillator circuits, you can alter the lowpass filters' gain so that the circuit's outputs deliver specific voltages, such as 1V p-p, at all frequencies.

　　Table 1 and Table 2, respectively, contain summaries of the phase-shift and quadrature oscillators' components and output characteristics. CN refers to the value of the capacitor used in the nth PAC block for oscillation at frequency f0. The design uses a Tektronix TDS1002 digital oscilloscope's FFT function to measure THD and the spectral line width of each output frequency at a level of –20 dB with respect to the central frequency, f0.

　　Figure 3 illustrates the application of a microcontroller to dynamically reconfigure an ispPAC-based oscillator for specific frequencies. The nonvolatile memory stores frequency-specific capacitance and gain values for each of the ispPAC10's circuit blocks. Data transfers occur using the IEEE 1149.1 JTAG-standard protocol through the ispPAC10's serial test-access-port interface.

　　References

　　PAC Designer software, www.latticesemi.com.

　　http://jlnlabs.imars.com/spgen/barkhausen.htm.