Yolo神經(jīng)網(wǎng)絡(luò)在集成電路焊盤布局規(guī)則檢測上的應(yīng)用研究
2022年電子技術(shù)應(yīng)用第7期
林純熙1,粟 濤2
1.北京郵電大學(xué) 國際學(xué)院,北京100001;2.中山大學(xué) 電子與信息工程學(xué)院,廣東 廣州510006
摘要: 為探索深度學(xué)習(xí)在集成電路設(shè)計自動化上的應(yīng)用,以電源和接地焊盤的排列規(guī)則作為檢查案例,研究了Yolo v3神經(jīng)網(wǎng)絡(luò)在版圖檢查上的可行性。采用Python腳本批量生成版圖樣本圖片,并使用LabelImg進(jìn)行標(biāo)簽標(biāo)記。使用TensorFlow框架編寫了基于Yolo v3的版圖檢查器。結(jié)果顯示,版圖檢查器在判斷焊盤布局正確性上實現(xiàn)了高精確率與高召回率。此外,還通過調(diào)整版圖的大小、形狀、對稱性與焊盤數(shù)目的方式對檢查器進(jìn)行了進(jìn)一步測試。檢查器仍表現(xiàn)卓越,體現(xiàn)出良好的擴展性。研究表明Yolo v3可以很好地找出焊盤布局的錯誤。深度學(xué)習(xí)在集成電路版圖檢查中的潛力大,值得繼續(xù)探索。
中圖分類號: TN402
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.212288
中文引用格式: 林純熙,粟濤. Yolo神經(jīng)網(wǎng)絡(luò)在集成電路焊盤布局規(guī)則檢測上的應(yīng)用研究[J].電子技術(shù)應(yīng)用,2022,48(7):40-43,48.
英文引用格式: Lin Chunxi,Su Tao. Rule check of pad placement in IC layout with Yolo[J]. Application of Electronic Technique,2022,48(7):40-43,48.
文獻(xiàn)標(biāo)識碼: A
DOI:10.16157/j.issn.0258-7998.212288
中文引用格式: 林純熙,粟濤. Yolo神經(jīng)網(wǎng)絡(luò)在集成電路焊盤布局規(guī)則檢測上的應(yīng)用研究[J].電子技術(shù)應(yīng)用,2022,48(7):40-43,48.
英文引用格式: Lin Chunxi,Su Tao. Rule check of pad placement in IC layout with Yolo[J]. Application of Electronic Technique,2022,48(7):40-43,48.
Rule check of pad placement in IC layout with Yolo
Lin Chunxi1,Su Tao2
1.International College,Beijing University of Posts and Telecommunications,Beijing 100001,China; 2.School of Electronics and Information Engineering,Sun Yat-sen University,Guangzhou 510006,China
Abstract: The application of deep learning on electronic design automation of integrated circuits is an interesting topic. This paper investigates the possibility of using Yolo v3 neural network to perform layout checks, which uses the arrangement rules between power and ground pads as inspection cases. In order to generate a training picture set, we use a custom Python script to generate layout sample pictures in batches and utilize LabelImg to label. The Yolo v3 layout checker is written under the TensorFlow framework. Evaluations demonstrate that the proposed layout checker achieves both high accuracy and high recall rate when judging the correctness of the pad layout. Additionally, the inspector is further tested by adjusting the size, shape, symmetry, and number of pads of the layout. Under such circumstances, the inspector still possesses an outstanding performance, showing great scalability. Our research reveals that the Yolo v3 neural network is able to find out errors in pad layout efficiently. Deep learning has great potential in integrated circuit layout inspection, which is worthy of further exploration.
Key words : integrated circuits;electronic design automation;layout check;deep learning;neural network
0 引言
從2015年以來,產(chǎn)業(yè)界研發(fā)了多種神經(jīng)網(wǎng)絡(luò)處理器[1-2],并使用這些處理器制造了許多服務(wù)器,在多個城市大規(guī)模地部署了計算中心[3-5]。這些服務(wù)器具有強大的計算力。大量的個人攜帶的移動終端也嵌入了帶神經(jīng)網(wǎng)絡(luò)處理器的芯片,形成一種隨處可用的算力。如果這些算力也可以參與到集成電路的自動化設(shè)計中來,那會使設(shè)計工作變得更加方便。比如說,只需要下載相應(yīng)的權(quán)值,就可以使用手機進(jìn)行集成電路設(shè)計版圖的檢查,這對管理人員也是一種幫助。
神經(jīng)網(wǎng)絡(luò)在圖像分析上獲得了巨大的成功。這些成功的案例有:目標(biāo)分類[6-8]、目標(biāo)檢測[9-12]、目標(biāo)識別[13-14]。除了單目標(biāo)分析,神經(jīng)網(wǎng)絡(luò)還可以進(jìn)行多目標(biāo)分析[15-16],比如在一張圖中找到所有汽車[17]。然而當(dāng)前成功的深度學(xué)習(xí)神經(jīng)網(wǎng)絡(luò)對于集成電路設(shè)計是否仍然有效,還有待研究。
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作者信息:
林純熙1,粟 濤2
(1.北京郵電大學(xué) 國際學(xué)院,北京100001;2.中山大學(xué) 電子與信息工程學(xué)院,廣東 廣州510006)
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