ST公司的 M24LR64-R是無線存儲器，具有口令保護(hù)的64Kb EEPROM以及400kHz I2C串行總線和13.56MHz ISO 15693 RF協(xié)議的 雙接口的64Kb EEPROM，可實(shí)現(xiàn)智能手機(jī)的近場通信（NFC）。單電源1.8V-5.5V工作，64kb EEPROM分成I2C模式的8192B和RF模式的2048x32b，無接觸接口和ISO 15693與ISO 18000-3 mode 1兼容，載波頻率13.56 MHz ±7k Hz，廣泛用于工業(yè)和消費(fèi)類電子產(chǎn)品。本文介紹了M24LR64-R 主要特性，方框圖，M24LR64-R單片和多組合參考設(shè)計以及雙接口EEPROM開發(fā)套件主要特性。

The M24LR64-R device is a dual-interface, electrically erasable programmable memory(EEPROM). It features an I2C interface and can be operated from a VCC power supply. It is also a contactless memory powered by the received carrier electromagnetic wave.

The M24LR64-R is organized as 8192 × 8 bits in the I2C mode and as 2048 × 32 bits in the ISO 15693 and ISO 18000-3 mode 1 RF mode.I2C uses a two-wire serial interface, comprising a bidirectional data line and a clock line. The devices carry a built-in 4-bit device type identifier code (1010) in accordance with the I2C bus definition.

The device behaves as a slave in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a Start condition, generated by the bus master. The Start condition is followed by a device select code and Read/Write bit (RW), terminated by an acknowledge bit.

When writing data to the memory, the device inserts an acknowledge bit during the 9th bit time, following the bus master’s 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a Stop condition after an Ack for Write, and after a NoAck for Read.In the ISO15693/ISO18000-3 mode 1 RF mode, the M24LR64-R is accessed via the 13.56 MHz carrier electromagnetic wave on which incoming data are demodulated from the received signal amplitude modulation (ASK: amplitude shift keying). The received ASK wave is 10% or 100% modulated with a data rate of 1.6 Kbit/s using the 1/256 pulse coding mode or a data rate of 26 Kbit/s using the 1/4 pulse coding mode.

Outgoing data are generated by the M24LR64-R load variation using Manchester coding with one or two subcarrier frequencies at 423 kHz and 484 kHz. Data are transferred from the M24LR64-R at 6.6 Kbit/s in low data rate mode and 26 Kbit/s high data rate mode. The M24LR64-R supports the 53 Kbit/s in high data rate mode in one subcarrier frequency at 423 kHz. The M24LR64-R follows the ISO 15693 and ISO 18000-3 mode 1 recommendation for radio-frequency power and signal interface.

M24LR64-R 主要特性：

I2C interface

■ Two-wire I2C serial interface supports 400 kHz protocol

■ Single supply voltage:

– 1.8 V to 5.5 V

■ Byte and Page Write (up to 4 bytes)

■ Random and Sequential Read modes

■ Self-timed programming cycle

■ Automatic address incrementing

■ Enhanced ESD/latch-up protection

Contactless interface

■ ISO 15693 and ISO 18000-3 mode 1 compatible

■ 13.56 MHz ±7k Hz carrier frequency

■ To tag: 10% or 100% ASK modulation using 1/4 (26 Kbit/s) or 1/256 (1.6 Kbit/s) pulse position coding

■ From tag: load modulation using Manchester coding with 423 kHz and 484 kHz subcarriers in low (6.6 kbit/s) or high (26 kbit/s) data rate mode. Supports the 53 kbit/s data rate with Fast commands

■ Internal tuning capacitance: 27.5 pF

■ 64-bit unique identifier (UID)

■ Read Block & Write (32-bit Blocks)

Memory

■ 64 Kbit EEPROM organized into:

– 8192 bytes in I2C mode

– 2048 blocks of 32 bits in RF mode

■ Write time

– I2C: 5 ms (Max.)

– RF: 5.75 ms including the internal Verify time

■ More than 1 Million write cycles

■ Multiple password protection in RF mode

■ Single password protection in I2C mode

■ More than 40-year data retention

■ Package

– ECOPACK2® (RoHS compliant and Halogen-free)

圖1。M24LR64-R方框圖

M24LR64-R多組合參考設(shè)計

M24LR64-R Multi-bank reference design description and settings

The M24LR64-R multi-bank reference design has been created to help users increase the memory density of their Dual Interface EEPROM, and has been designed in a way that will minimize the antenna size and the I²C interface footprint on the PCB.

The basic principle is to connect several M24LR64-R devices in parallel on the same I²C bus (in compliance with I²C specifications) and for them to share one single antenna.

This application note describes how the M24LR64-R Multi-Bank reference design works from the schematics and design perspective, and explains how to configure and use it.

The ANT5-M24LR-A reference design consists of four M24LR64-R devices in parallel, resulting in 256 Kbits of equivalent user memory. The equivalent tuning capacitance value is 4 times that of a single M24LR64-R device. So the antenna, whether it is designed on a PCB or uses an SMD inductor, must be 4 times smaller than the one used for one single M24LR64-R device.


圖2。ANT1-M24LR-A參考設(shè)計框圖

圖3。ANT5-M24LR-A參考設(shè)計框圖

M24LR64-R雙接口EEPROM開發(fā)套件

The DEVKIT-M24LR-A is a development kit for ST Dual Interface EEPROM products which allows system designers to evaluate the I2C and RF performance and capabilities of the M24LR64-R.

RF applications can be developed using the ISO15693 13.56 MHz RF reader.

雙接口EEPROM開發(fā)套件主要特性：

■ Middle-range RF reader (ISO 15693, RF 13.56 MHz) interfaced via the USB bus

■ External RF reader antenna

■ Serial EEPROM USB reader interfaced through the USB bus

■ ANT1-M24LR-A antenna reference board

■ I2C cable to connect the serial EEPROM USB reader to the ANT1-M24LR-A

■ External power supply

■ Installation CD-ROM including

– Technical documentation

– Installation software PC software

圖4。M24LR64-R雙接口EEPROM開發(fā)套件外形圖
詳情請見：
http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/USER_MANUAL/CD00254727.pdf
和
http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/APPLICATION_NOTE/CD00280653.pdf