XILINX FPGA的時(shí)序約束設(shè)計(jì)
所屬分類：參考設(shè)計(jì)
上傳者：nuanyangyang
文檔大?。?span>1360 K
標(biāo)簽： FPGA
所需積分：0分積分不夠怎么辦？
文檔介紹：Timing constraints may be applied to a schematic using the timespec ? symbol (FROM:TO’s) if your compiler supports them They can be added to HDL source code ? called a .UCF (user constraints file), They can be input in a separate file ? constraints file) or a synthesizer generated .NCF (netlist ile). f the PCF (physical constraints Some constraints must be placed in ? Normally, the PCF should be avoided by users.
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