中圖分類號： TN492
文獻(xiàn)標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.211421
中文引用格式： 葉豐華，劉昊，康磊，等. Buck芯片緩沖電路設(shè)計(jì)的仿真分析與應(yīng)用[J].電子技術(shù)應(yīng)用，2021，47(10)：113-117，123.
英文引用格式： Ye Fenghua，Liu Hao，Kang Lei，et al. Simulation analysis and application of buck chip buffer circuit design[J]. Application of Electronic Technique，2021，47(10)：113-117，123.

Simulation analysis and application of buck chip buffer circuit design

Abstract： The switching point of the buck converter is the main object of external tuning. With the increase of the switching frequency and the increase of the load current, the parasitic inductance in the chip has an increasing influence on the switching voltage waveform, and the external buffer circuit is used as the adjustment switch. The waveform tool plays a key role, and only relying on experience to design the external buffer circuit can no longer meet the design requirements. By analyzing the working principle of the buffer circuit, combined with simulation results and engineering practice, this paper analyzes the voltage regulation performance and efficiency loss of the buffer circuit, and provides a quantitative analysis method for the design of the peripheral buffer circuit.

Key words : buck converter；simulation；snubber；efficiency