基于Cadence CHI和IVD VIP的 多核SoC系統(tǒng)數(shù)據(jù)一致性驗證
2020年電子技術(shù)應(yīng)用第8期
范君健1，晁張虎1，楊慶娜1，劉 琪1，朱 紅1，單建旗2
1.天津飛騰信息技術(shù)有限公司，天津102209；2 Cadence，廣東 深圳518040
摘要： 在多核的SoC系統(tǒng)中，不同的處理器核對內(nèi)存空間和設(shè)備空間進(jìn)行著大量的數(shù)據(jù)讀寫操作，維護(hù)Cache一致性面臨嚴(yán)峻挑戰(zhàn)。集中于控制流方面的驗證環(huán)境搭建已非常復(fù)雜，而包含數(shù)據(jù)正確性檢查的驗證由于控制流程復(fù)雜、數(shù)據(jù)量大等問題而更加困難。針對這一問題，基于Cadence公司提供CHI VIP、AXI VIP和IVD VIP，實現(xiàn)多核環(huán)境下的系統(tǒng)級數(shù)據(jù)一致性驗證。搭建的驗證平臺中采用CHI VIP通過筆者開發(fā)的CHI協(xié)議轉(zhuǎn)換橋發(fā)出訪存請求，使用AXI VIP收集到達(dá)主存的數(shù)據(jù)，由IVD VIP對CHI端口的請求數(shù)據(jù)與AXI端口的訪存數(shù)據(jù)進(jìn)行實時分析比對，實現(xiàn)在較高抽象層次上的激勵產(chǎn)生和響應(yīng)檢查。該驗證平臺能夠在子系統(tǒng)級及系統(tǒng)級進(jìn)行數(shù)據(jù)一致性驗證，具有驗證環(huán)境搭建快速和功能點覆蓋完備的優(yōu)點。
中圖分類號： TN409
文獻(xiàn)標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.209805
中文引用格式： 范君健，晁張虎，楊慶娜，等. 基于Cadence CHI和IVD VIP的多核SoC系統(tǒng)數(shù)據(jù)一致性驗證[J].電子技術(shù)應(yīng)用，2020，46(8)：72-76.
英文引用格式： Fan Junjian，Chao Zhanghu，Yang Qingna，et al. Multi-core SoC based on Cadence CHI and IVD VIP system data coherence verification[J]. Application of Electronic Technique，2020，46(8)：72-76.
文獻(xiàn)標(biāo)識碼： A
DOI：10.16157/j.issn.0258-7998.209805
中文引用格式： 范君健，晁張虎，楊慶娜，等. 基于Cadence CHI和IVD VIP的多核SoC系統(tǒng)數(shù)據(jù)一致性驗證[J].電子技術(shù)應(yīng)用，2020，46(8)：72-76.
英文引用格式： Fan Junjian，Chao Zhanghu，Yang Qingna，et al. Multi-core SoC based on Cadence CHI and IVD VIP system data coherence verification[J]. Application of Electronic Technique，2020，46(8)：72-76.
Multi-core SoC based on Cadence CHI and IVD VIP system data coherence verification
Fan Junjian1，Chao Zhanghu1，Yang Qingna1，Liu Qi1，Zhu Hong1，Shan Jianqi2
1.Tianjin Phytium Technology Co.，Ltd.，Tianjin 102209，China；2.Cadence，Shenzhen 518040，China
Abstract： In a multi-core SoC system, different processor cores perform a large amount of data read and write operations on memory space and device space. Maintaining cache coherence is facing severe challenges. The verification environment focused on the control flow has been very complicated, and the verification including data correctness check is more difficult due to the complicated control process and large amount of data. In response to this problem, this paper is based on Cadence CHI VIP, AXI VIP and IVD VIP to achieve system-level data coherence verification in a multi-core environment. In this paper, CHI VIP is used to issue a memory access request through the CHI protocol conversion bridge developed by the author, and AXI VIP is used to collect data that arrives in the main memory, real-time analysis and comparison of the request data of the CHI port and the access data of the AXI port by the IVD VIP，to realize stimulus generation and response inspection at a higher level of abstraction. The verification platform can perform data consistency verification at the subsystem level and system level, and has the advantages of rapid verification environment construction and complete coverage of function points.
Key words : cache coherence；subsystem verification；VIP；modular verification
0 引言
Cache(高速緩沖存儲器)是存在于處理器核與主存之間的存儲器，在多核的處理器系統(tǒng)當(dāng)中，當(dāng)多個Cache包含同一塊數(shù)據(jù)時，如果其中任意一個Cache修改了該數(shù)據(jù)塊而沒有通知其他的Cache，就會產(chǎn)生數(shù)據(jù)不一致的情況[1]。Cache一致性就是維護(hù)多個Cache數(shù)據(jù)的一致性，Cache一致性協(xié)議是多核處理器系統(tǒng)的核心，因此Cache一致性的驗證是一項非常重要的工作。
現(xiàn)階段，Cache一致性的驗證一般采用軟件模擬的形式，但隨著協(xié)議復(fù)雜性的增加，驗證中需要覆蓋的狀態(tài)與路徑成幾何倍數(shù)增加。同時，訪存數(shù)據(jù)在經(jīng)過片上互聯(lián)網(wǎng)絡(luò)寫入主存時要經(jīng)過較長的路徑，需要對流經(jīng)網(wǎng)絡(luò)的數(shù)據(jù)正確性進(jìn)行檢查，驗證環(huán)境的復(fù)雜程度越來越高。在驗證環(huán)境搭建與驗證覆蓋率收集方面，驗證人員往往需要投入大量的精力，導(dǎo)致Cache一致性驗證周期耗時較長。
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作者信息:
范君健1，晁張虎1，楊慶娜1，劉 琪1，朱 紅1，單建旗2
(1.天津飛騰信息技術(shù)有限公司，天津102209；2 Cadence，廣東 深圳518040)
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